H01L29/4908

Semiconductor device comprising oxide semiconductor with c-axis-aligned crystals

An embodiment is a semiconductor device which includes a first oxide semiconductor layer over a substrate having an insulating surface and including a crystalline region formed by growth from a surface of the first oxide semiconductor layer toward an inside; a second oxide semiconductor layer over the first oxide semiconductor layer; a source electrode layer and a drain electrode layer which are in contact with the second oxide semiconductor layer; a gate insulating layer covering the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer; and a gate electrode layer over the gate insulating layer and in a region overlapping with the second oxide semiconductor layer. The second oxide semiconductor layer is a layer including a crystal formed by growth from the crystalline region.

Semiconductor device

A semiconductor device that is suitable for miniaturization and higher density is provided. A semiconductor device includes a first transistor over a semiconductor substrate, a second transistor including an oxide semiconductor over the first transistor, and a capacitor over the second transistor. The capacitor includes a first conductor, a second conductor, and an insulator. The second conductor covers a side surface of the first conductor with an insulator provided therebetween.

Organic Light Emitting Display Device Comprising Multi-Type Thin Film Transistor and Method of Manufacturing the Same
20180012947 · 2018-01-11 ·

An organic light emitting display device includes a driving TFT on the substrate, a switching TFT on the substrate, and an organic light emitting diode. The driving TFT includes a first active layer formed of poly-Si, and at least a first part of an interlayer insulation layer on the first active layer. The interlayer insulation layer is formed of a first material including hydrogen. The switching TFT includes a second active layer, at least a second part of the interlayer insulation layer between the first active layer and the second active layer, and at least a part of a gate insulation layer between the second part of the interlayer insulation layer and the second active layer. The gate insulation layer is formed from a second material different from the first material and blocking diffusion of hydrogen from the interlayer insulation layer to the second active layer.

Gate-all-around device with trimmed channel and dipoled dielectric layer and methods of forming the same

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

Semiconductor device and display device
11710746 · 2023-07-25 · ·

The semiconductor device comprises a gate electrode, a first gate insulating film overlapping a part of the side surface and the upper surface of the gate electrode, a second gate insulating film overlapping the upper surface of the gate electrode, a semiconductor film provided on the upper surface of the second gate insulating film and overlapping the gate electrode and a first terminal and a second terminal overlapping the upper surface of the semiconductor film. In a plan view, a first region is a region where the semiconductor film overlaps the upper surface of the first gate insulating film and the second gate insulating film between the first terminal and the second terminal, and a third region is a region that overlaps both a part of the upper surface of the gate electrode and the second gate insulating film and does not overlap the first gate insulating film.

Semiconductor device and manufacturing method thereof

An oxide semiconductor layer which is intrinsic or substantially intrinsic and includes a crystalline region in a surface portion of the oxide semiconductor layer is used for the transistors. An intrinsic or substantially intrinsic semiconductor from which an impurity which is to be an electron donor (donor) is removed from an oxide semiconductor and which has a larger energy gap than a silicon semiconductor is used. Electrical characteristics of the transistors can be controlled by controlling the potential of a pair of conductive films which are provided on opposite sides from each other with respect to the oxide semiconductor layer, each with an insulating film arranged therebetween, so that the position of a channel formed in the oxide semiconductor layer is determined.

INSULATING FILM, METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE, AND SEMICONDUCTOR DEVICE

In a semiconductor device including a transistor including an oxide semiconductor film and a protective film over the transistor, an oxide insulating film containing oxygen in excess of the stoichiometric composition is formed as the protective film under the following conditions: a substrate placed in a treatment chamber evacuated to a vacuum level is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C.; a source gas is introduced into the treatment chamber so that the pressure in the treatment chamber is set to be higher than or equal to 100 Pa and lower than or equal to 250 Pa; and a high-frequency power higher than or equal to 0.17 W/cm.sup.2 and lower than or equal to 0.5 W/cm.sup.2 is supplied to an electrode provided in the treatment chamber.

TRANSISTOR INCLUDING WRAP AROUND SOURCE AND DRAIN CONTACTS

A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.

SEMICONDUCTOR DEVICE

A semiconductor device may include a substrate including first and second active regions, which are adjacent to each other, first and second active patterns provided on the first and second active regions, respectively, and a gate electrode extended to cross the first and second active patterns. The gate electrode may include first and second electrode portions provided on the first and second active regions, respectively. The second electrode portion may include a first metal pattern, an etch barrier pattern, a second metal pattern, and a third metal pattern sequentially covering the second active pattern. The first electrode portion may include a second metal pattern covering the first active pattern. The etch barrier pattern may be in contact with the first metal pattern and the second metal pattern, and the etch barrier pattern may be thinner than the first metal pattern and thinner than the second metal pattern.

TRANSISTOR

A transistor includes an oxide semiconductor layer, a source electrode and a drain electrode disposed spaced apart from each other on the oxide semiconductor layer, a gate electrode spaced apart from the oxide semiconductor layer, a gate insulating layer disposed between the oxide semiconductor layer and the gate electrode, and a graphene layer disposed between the gate electrode and the gate insulating layer and doped with a metal.