A semiconductor device includes: a substrate including an active region and a device isolation region; a flat plate structure formed on the substrate; an oxide semiconductor layer covering a top surface of the flat plate structure and continuously arranged on a top surface of the substrate in the active region and the device isolation region; a gate structure arranged on the oxide semiconductor layer and including a gate dielectric layer and a gate electrode; and a source/drain region arranged on both sides of the gate structure and formed in the oxide semiconductor layer, in which, when viewed from a side cross-section, an extending direction of the flat plate structure and an extending direction of the gate structure cross each other.

A semiconductor structure that includes a first semiconductor fin and a second semiconductor fin disposed over a substrate and adjacent to each other, a metal gate stack disposed over the substrate, and source/drain features disposed in each of the first semiconductor fin and the second semiconductor fin to engage with the metal gate stack. The metal gate stack includes a first region disposed over the first semiconductor fin, a second region disposed over the second semiconductor fin, and a third region connecting the first region to the second region in a continuous profile, where the first region is defined by a first gate length and the second region is defined by a second gate length less than the first gate length.

Semiconductor device and the manufacturing method thereof are disclosed. An exemplary method comprises forming a first stack structure and a second stack structure in a first area over a substrate, wherein each of the stack structures includes semiconductor layers separated and stacked up; depositing a first interfacial layer around each of the semiconductor layers of the stack structures; depositing a gate dielectric layer around the first interfacial layer; forming a dipole oxide layer around the gate dielectric layer; removing the dipole oxide layer around the gate dielectric layer of the second stack structure; performing an annealing process to form a dipole gate dielectric layer for the first stack structure and a non-dipole gate dielectric layer for the second stack structure; and depositing a first gate electrode around the dipole gate dielectric layer of the first stack structure and the non-dipole gate dielectric layer of the second stack structure.

A semiconductor structure and a method for forming the same are provided. One form of a method includes: forming a source/drain groove in the channel structure on two sides of a gate structure; forming a sacrificial epitaxial layer on a bottom of the source/drain groove; forming, on the sacrificial epitaxial layer, a source/drain doped layer in the source/drain groove; and removing the sacrificial epitaxial layer, to form a gap between a bottom of the source/drain doped layer and the protrusion. After the sacrificial epitaxial layer is formed, the source/drain doped layer located in the source/drain groove may be formed on the sacrificial epitaxial layer using the epitaxy process on the basis of the sacrificial epitaxial layer. Therefore, the epitaxy process for forming the source/drain doped layer is prevented from adverse effects, the epitaxial growth quality of the source/drain doped layer is ensured, and a performance of the semiconductor structure is optimized.

A semiconductor device includes an active region in a substrate, at least one nano-sheet on the substrate and spaced apart from a top surface of the active region, a gate above or below the nano-sheet, a gate insulating layer between the at least one nano-sheet and the gate, and source/drain regions on the active region at both sides of the at least one nano-sheet. The at least one nano-sheet includes a channel region; a gate disposed above or below the nano-sheet and including a single metal layer having different compositions of metal atoms of a surface and an inside thereof; a gate insulating layer between the nano-sheet and the gate; and source/drain regions disposed in the active region of both sides of the at least one nano-sheet.

The present disclosure provides a thin-film transistor and a method for manufacturing the same, an array substrate, and a display device. The thin film transistor of the present disclosure include a plurality of insulating layers, among which at least one insulating layer on the low temperature polysilicon layer comprises organic material, so vias could be formed in the organic material by an exposing and developing process, thereby effectively avoiding the over-etching problem of the low temperature polycrystalline silicon layer caused by dry etching process. By adopting the method for manufacturing the film transistors of the present disclosure, the contact area and uniformity of the drain electrode and the low temperature polysilicon material layer can be increased; the conductivity can be improved; and the production cycle of products can be greatly reduced and thereby improving the equipment capacity.

According to one embodiment, a method of manufacturing a semiconductor device, includes forming a first insulating layer, an oxide semiconductor layer, a second insulating layer, a buffer layer and a metal layer sequentially on a base, forming a patterned resist on the metal layer, etching the buffer layer and the metal layer using the resist as a mask to expose an upper surface of the second insulating layer, reducing a volume of the resist to expose an upper surface along a side surface of the metal layer, etching the metal layer using the resist as a mask, to form a gate electrode and to expose an upper surface of the buffer layer, and carrying out ion implantation on the oxide semiconductor layer using the gate electrode as a mask.

Provided is a field effect transistor including a gate insulating layer having a two-dimensional material. The field effect transistor may include a first channel layer; a second channel layer disposed on the first channel layer; a gate insulating layer disposed on the second channel layer; a gate electrode disposed on the gate insulating layer; a first electrode electrically connected to the first channel layer; and a second electrode electrically connected to the second channel layer. Here, the gate insulating layer may include an insulative, high-k, two-dimensional material.

A semiconductor device includes a substrate having at least a trench formed therein. A conductive material fills a lower portion of the trench. A barrier layer is between the conductive material and the substrate. An insulating layer is in the trench and completely covers the conductive material and the barrier layer, wherein a portion of the insulating layer covering the barrier layer has a bird's peak profile.

Transistors with metal oxide channel material and a multi-composition gate dielectric. A surface of a metal oxide gate dielectric may be nitrided before deposition of a metal oxide channel material, for example to reduce gate capacitance of a TFT. Breakdown voltage and/or drive current of a TFT can be increased through the introduction of an additional metal oxide and/or nitride between the gate electrode and a metal oxide gate dielectric. The introduction of an intervening layer between two layers of a metal oxide gate dielectric can also increase breakdown voltage and/or drive current of a TFT.