A semiconductor device includes a semiconductor substrate, multiple trench gate structures and an emitter region. The semiconductor substrate includes: a drift layer of a first conductivity type; a base layer of a second conductivity type disposed on the drift layer; and a collector layer of the second conductivity type, the collector layer disposed at a position opposite to the base layer with the drift layer sandwiched between the base layer and the collector layer. Each of the trench gate structures includes: a trench penetrating the base layer and reaching the drift layer; a gate insulation film is disposed at a wall surface of the trench; and a gate electrode disposed on the gate insulation film. The emitter region is disposed on a surface layer portion of the base layer and is in contact with the trench.

Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. Each memory cell structure of the plurality of memory cell structures comprises a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with a sidewall surface of the select gate electrode within the memory region. A lower inter-layer dielectric layer is disposed on the CESL between the plurality of memory cell structures within the memory region.

A semiconductor structure for a memory device includes a first gate structure and a second gate structure adjacent to the first gate structure. The second gate structure includes a first layer and a second layer, and the first layer is between the second layer and the first gate structure. The first layer and the second layer include a same semiconductor material and same dopants. The first layer has a first dopant concentration, and the second layer has a second dopant concentration different from the firs dopant concentration.

An integrated circuit includes a high-voltage MOS (HV) transistor and a capacitor supported by a semiconductor substrate. A gate stack of the HV transistor includes a first insulating layer over the semiconductor layer and a gate electrode formed from a first polysilicon. The capacitor includes a first electrode made of the first polysilicon and a second electrode made of a second polysilicon and at least partly resting over the first electrode. A first polysilicon layer deposited over the semiconductor substrate is patterned to form the first polysilicon of the gate electrode and first electrode, respectively. A second polysilicon layer deposited over the semiconductor substrate is patterned to form the second polysilicon of the second electrode. Silicon oxide spacers laterally border the second electrode and the gate stack of the HV transistor. Silicon nitride spacers border the silicon oxide spacers.

FET designs that exhibit low leakage in the presence of the edge transistor phenomenon. Embodiments includes nFET designs in which the work function Φ.sub.MF of the gate structure overlying the edge transistors of the nFET is increased by forming extra P+ implant regions within at least a portion of the gate structure, thereby increasing the Vt of the edge transistors to a level that may exceed the Vt of the central conduction channel of the nFET. In some embodiments, the gate structure of the nFET is modified to increase or “flare” the effective channel length of the edge transistors relative to the length of the central conduction channel of the FET. Other methods of changing the work function Φ.sub.MF of the gate structure overlying the edge transistors are also disclosed. The methods may be adapted to fabricating pFETs by reversing or substituting material types.

Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A memory cell structure is disposed on the memory region. A logic device is disposed on the logic region having a logic gate electrode separated from the substrate by a logic gate dielectric. A sidewall spacer is disposed along a sidewall surface of the logic gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with sidewall surfaces of the pair of select gate electrodes within the memory region, and extending upwardly along the sidewall spacer within the logic region.

The integrated circuit includes a logic part including standard cells arranged in parallel rows along a first direction and in an alternation of complementary semiconductor wells. Among the standard cells, at least one capacitive filling structure belongs to two adjacent rows and includes a capacitive interface between a conductive armature and the first well, the extent of the second well in the first direction being interrupted over the length of the capacitive filling structure so that the first well occupies in the second direction the width of the two adjacent rows of the capacitive filling structure. A conductive structure electrically connects the second well on either side of the capacitive filling structure.

Embodiments provide a semiconductor structure and a method for fabricating a semiconductor structure. The semiconductor structure includes: a source region and a drain region arranged at intervals on a substrate; a gate oxide layer arranged between the source region and the drain region; a gate structure arranged on the gate oxide layer; and a conductive plug arranged at a corresponding location of the source region and a corresponding location of the drain region. The gate structure includes a plurality of conductive layers, at least one target conductive layer is present in the plurality of conductive layers, and a distance from the at least one target conductive layer to the conductive plug is greater than a distance from at least one adjacent layer of the target conductive layer to the conductive plug.

A drift layer is formed over a semiconductor substrate which is an SiC substrate. The drift layer includes first to third n-type semiconductor layers and a p-type impurity region. Herein, an impurity concentration of the second n-type semiconductor layer is higher than an impurity concentration of the first n-type semiconductor layer and an impurity concentration of the third n-type semiconductor layer. Also, in plan view, the second semiconductor layer located between the p-type impurity regions adjacent to each other overlaps with at least a part of a gate electrode formed in a trench.

Systems and methods for building passive and active electronics with diamond-like carbon (DLC) coatings are provided herein. DLC may be layered upon substrates to form various components of electronic devices. Passive components such as resistors, capacitors, and inductors may be built using DLC as a dielectric or as an insulating layer. Active components such as diodes and transistors may be built with the DLC acting substantially like a semiconductor. The amount of sp.sup.2 and sp.sup.3 bonded carbon atoms may be varied to modify the properties of the DLC for various electronic components.