III-Nitride heterostructures with low p-type sheet resistance and III-Nitride heterostructure devices with gate recess and devices including the III-Nitride heterostructures are disclosed.

A silicon carbide (SiC) metal oxide semiconductor (MOS) power device is disclosed which includes an SiC drain semiconductor region, an SiC drift semiconductor region coupled to the SiC drain semiconductor region, an SiC base semiconductor region coupled to the SiC drift semiconductor region, an SiC source semiconductor region coupled to the SiC base semiconductor region, a source electrode coupled to the SiC source semiconductor region, a drain electrode coupled to the SiC drain semiconductor region, a gate electrode, wherein voltage of the gate electrode with respect to the SiC base semiconductor region is less than or equal to about 12 V and thickness of the dielectric material is such that the electric field in the dielectric material is about 4 MV/cm when said gate voltage is about 12 V.

A capacitor is provided for high temperature systems. The capacitor includes: a substrate formed from silicon carbide material; a dielectric stack layer, including a first layer deposited on the substrate and a second layer deposited on the first layer; a Schottky contact layer deposited on the second layer; and an Ohmic contact layer deposited on the substrate. The first layer is formed with aluminum nitride (AlN) epitaxially, and the second layer is formed with aluminum oxide (Al.sub.2O.sub.3). AlN and Al.sub.2O.sub.3 are ultrawide band gap materials, and as a result, they can be use as the dielectric in the capacitor, allowing the capacitance changes to be less than 10% between −250° C. and 600° C., which is very effective for the high temperature systems.

Disclosed herein are IC structures that implement field plates for III-N transistors in a form of electrically conductive structures provided in a III-N semiconductor material below the polarization layer (i.e., at the “backside” of an IC structure). In some embodiments, such a field plate may be implemented as a through-silicon via (TSV) extending from the back/bottom face of the substrate towards the III-N semiconductor material. Implementing field plates at the backside may provide a viable approach to changing the distribution of electric field at a transistor drain and increasing the breakdown voltage of an III-N transistor without incurring the large parasitic capacitances associated with the use of metal field plates provided above the polarization material. In addition, backside field plates may serve as a back barrier for advantageously reducing drain-induced barrier lowering.

A method of manufacturing a semiconductor device, including: forming a dielectric layer configured to be a gate oxide contacting the second well on the substrate, wherein the dielectric layer is single-layered dielectric layer and includes a contact via penetrating through the dielectric layer; and forming a patterned conductive layer contacting the dielectric layer, wherein the patterned conductive layer includes a first conductive portion isolated from the second well and configured to be a gate electrode, and a second conductive portion coupled to the first well via the contact via; wherein the first conductive portion is leveled with the second conductive portion, and the first conductive portion and the second conductive portion are formed entirely on a topmost surface of the dielectric layer; wherein the dielectric layer and the first conductive portion collectively serve as a gate of the transistor, and the transistor is configured as a high-voltage transistor.

A semiconductor device includes a substrate, a fin structure and an isolation layer formed on the substrate and adjacent to the fin structure. The semiconductor device includes a gate structure formed on at least a portion of the fin structure and the isolation layer. The semiconductor device includes an epitaxial layer including a strained material that provides stress to a channel region of the fin structure. The epitaxial layer has a first region and a second region, in which the first region has a first doping concentration of a first doping agent and the second region has a second doping concentration of a second doping agent. The first doping concentration is greater than the second doping concentration. The epitaxial layer is doped by ion implantation using phosphorous dimer.

Embodiments of the invention are directed to a transistor device that includes a channel stack having stacked, spaced-apart, channel layers. A first source or drain (S/D) region is communicatively coupled to the channel stack. A tunnel extends through the channel stack, wherein the tunnel includes a central region and a first set of end regions. The first set of end regions is positioned closer to the first S/D region than the central region is to the first S/D region. A first type of work-function metal (WFM) is formed in the first set of end regions, the first WFM having a first work-function (WF). A second type of WFM is formed in the central region, the second type of WFM having a second WF, wherein the first WF is different than the second WF.

A semiconductor device includes an active region spanning along a first direction. The semiconductor device includes a first elongated gate spanning along a second direction substantially perpendicular to the first direction. The first elongated gate includes a first portion that is disposed over the active region and a second portion that is not disposed over the active region. The first portion and the second portion include different materials. The semiconductor device includes a second elongated gate spanning along the second direction and separated from the first elongated gate in the first direction. The second elongated gate includes a third portion that is disposed over the active region and a fourth portion that is not disposed over the active region. The third portion and the fourth portion include different materials.

An IC structure comprises a substrate, a first SRAM cell, and a second SRAM cell. The first SRAM cell is formed over the substrate and comprises a first N-type transistor. The second SRAM cell is formed over the substrate and comprises a second N-type transistor. A gate structure of first N-type transistor of the first SRAM cell has a different work function metal composition than a gate structure of the second N-type transistor of the second SRAM cell.

A semiconductor device that can have an improved data retention characteristic is provided. A semiconductor device includes a stacked body and a memory pillar formed in a memory hole of the stacked body. The memory pillar has a structure in which a semiconductor portion 61b, a tunnel insulating film 62a, and a charge storage layer 62b are sequentially stacked. A block insulating film 53 is provided between the charge storage layer 62b and a conductive layer 52. The conductive layer 52 contains molybdenum. The block insulating film 53 includes a silicon oxide film 53a and an aluminum oxide film 53b. A region from the conductive layer 52 to the aluminum oxide film 53b contains chlorine, which prevents OH diffusion. The concentration of chlorine at a second portion closer to the aluminum oxide film 53b than a first portion in the conductive layer 52 is higher than the concentration of impurities at the first portion in the conductive layer.