A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.

In an embodiment, a device includes: a gate structure over a substrate; a gate spacer adjacent the gate structure; a source/drain region adjacent the gate spacer; a first inter-layer dielectric (ILD) on the source/drain region, the first ILD having a first concentration of an impurity; and a second ILD on the first ILD, the second ILD having a second concentration of the impurity, the second concentration being less than the first concentration, top surfaces of the second ILD, the gate spacer, and the gate structure being coplanar; and a source/drain contact extending through the second ILD and the first ILD, the source/drain contact coupled to the source/drain region.

Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell along with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.

A field effect device is provided. The field effect device includes a semiconductor nanosheet segment above a substrate, and a T-shaped inner spacer on the semiconductor nanosheet segment. The field effect device further includes a gate dielectric layer on the semiconductor nanosheet segment, and a first work function material plug on the gate dielectric layer. The field effect device further includes a second work function material layer on the first work function material plug and a center portion of the gate dielectric layer, wherein the second work function material layer is a different work function material from the first work function material plug.

A semiconductor device includes a field insulating film including a first region and a second region on a substrate, a recess in the first region of the field insulating film, a gate electrode on the second region of the field insulating film, and a gate spacer along a sidewall of the gate electrode and a sidewall of the recess.

A method includes removing a first portion of a gate layer of a first transistor and leaving a second portion of the gate layer. The first transistor includes a drain region, a source region, and a gate stack, and the gate stack includes a gate dielectric layer, a gate conductive layer over the gate dielectric layer, and the gate layer directly on the gate conductive layer. The method includes removing a gate layer of a second transistor and forming a conductive region at a region previously occupied by the first portion of the gate layer of the first transistor, the unit resistance of the conductive region being less than that of the gate layer of the first transistor.

Disclosed are methods and systems for providing silicon carbide films. A layer of silicon carbide can be provided under process conditions that employ one or more silicon-containing precursors that have one or more silicon-hydrogen bonds and/or silicon-silicon bonds. The silicon-containing precursors may also have one or more silicon-oxygen bonds and/or silicon-carbon bonds. One or more radical species in a substantially low energy state can react with the silicon-containing precursors to form the silicon carbide film. The one or more radical species can be formed in a remote plasma source.

The present disclosure provides a semiconductor device capable of improving element performance and reliability. The semiconductor device comprises a lower wiring structure, an upper interlayer insulating layer disposed on the lower wiring structure and including an upper wiring trench, the upper wiring trench exposing a portion of the lower wiring structure, and an upper wiring structure including an upper liner and an upper filling layer on the upper liner in the upper wiring trench, wherein the upper liner includes a sidewall portion extending along a sidewall of the upper wiring trench and a bottom portion extending along a bottom surface of the upper wiring trench, the sidewall portion of the upper liner includes cobalt (Co) and ruthenium (Ru), and the bottom portion of the upper liner is formed of cobalt (Co).

Self-aligned gate endcap (SAGE) architectures having gate or contact plugs, and methods of fabricating SAGE architectures having gate or contact plugs, are described. In an example, an integrated circuit structure includes a first gate structure over a first semiconductor fin. A second gate structure is over a second semiconductor fin. A gate endcap isolation structure is between the first and second semiconductor fins and laterally between and in contact with the first and second gate structures. A gate plug is over the gate endcap isolation structure and laterally between the first gate structure and the second gate structure. A crystalline metal oxide material is laterally between and in contact with the gate plug and the first gate structure, and laterally between and in contact with the gate plug and the second gate structure.

The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.