A vertical field-effect transistor (VFET) includes: a fin structure on a substrate; a gate structure including a gate dielectric layer on an upper portion of a sidewall of the fin structure, and a conductor layer on a lower portion of the gate dielectric layer; a top source/drain (S/D) region above the fin structure and the gate structure; a bottom S/D region below the fin structure and the gate structure; a top spacer on an upper portion of the gate dielectric layer, and between the top S/D region and a top surface of the conductor layer; and a bottom spacer between the gate structure and the bottom S/D region. A top surface of the gate dielectric layer is positioned at the same or substantially same height as or positioned lower than a top surface of the top spacer, and higher than the top surface of the conductor layer.

Disclosed are semiconductor devices including a double gate metal oxide semiconductor (MOS) transistor and methods for fabricating the same. The double gate MOS transistor includes a first back gate, a second back gate, and a first dielectric layer disposed on the first back gate and on the second back gate. An MX2 material layer is disposed on the first dielectric layer, a second dielectric layer disposed on the MX2 material layer, and a work function metal (WFM) is disposed on the second dielectric layer. A front gate is disposed on the WFM, which fills a space between the first back gate and the second back.

A pixel cell includes a nitrogen-implanted region at a semiconductor material-gate oxide proximate interface located in a region above a photodiode. The pixel cell is further devoid of implanted nitrogen in channel regions of a plurality of pixel transistors. Thus, Si—N bonds are formed at the semiconductor material-gate oxide interface in the region above the photodiode, while the channel regions are protected from nitrogen implantation at the semiconductor material-gate oxide interface. Methods of forming the pixel cell are also described.

A semiconductor structure includes vertical stacks located over a substrate, wherein each of the vertical stacks includes from bottom to top, a bottom electrode, a dielectric pillar structure including a lateral opening therethrough, and a top electrode; layer stacks located over the vertical stacks, wherein each of the layer stacks includes an active layer and an outer gate dielectric and laterally surrounds a respective one of the vertical stacks; inner gate electrodes passing through a respective subset of the lateral openings in a respective row of vertical stacks that are arranged along a first horizontal direction; and outer gate electrodes laterally extending along the first horizontal direction and laterally surrounding a respective row of layer stacks.

A method for processing an integrated circuit includes forming I/O gate all around transistors and core gate all around transistors. The method performs a regrowth process on an interfacial gate dielectric layer of the I/O gate all around transistors by diffusing metal atoms into the interfacial dielectric layer I/O gate all around transistor. The regrowth process does not diffuse metal atoms into the interfacial gate dielectric layer of the gate all around core transistor.

A device comprises a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure comprises a first dielectric layer comprising a first dielectric material including dopants. A second dielectric layer is on the first dielectric layer, and comprises a second dielectric material substantially free of the dopants. A metal fill layer is over the second dielectric layer.

A layer structure including a dielectric layer, a method of manufacturing the layer structure, and an electronic device including the layer structure are disclosed. The layer structure including a lower layer, a dielectric layer, and an upper layer sequentially stacked. The dielectric layer includes sequentially stacked first, second, and third layers, wherein one of the first layer or the third layer is a ferroelectric, the other one is an antiferroelectric, and the second layer is an oxide layer. In one example, the dielectric layer may further include a fourth layer on the third layer.

A method used in forming an electronic component comprising conductive material and ferroelectric material comprises forming a non-ferroelectric metal oxide-comprising insulator material over a substrate. A composite stack comprising at least two different composition non-ferroelectric metal oxides is formed over the substrate. The composite stack has an overall conductivity of at least 1×10.sup.2 Siemens/cm. The composite stack is used to render the non-ferroelectric metal oxide-comprising insulator material to be ferroelectric. Conductive material is formed over the composite stack and the insulator material. Ferroelectric capacitors and ferroelectric field effect transistors independent of method of manufacture are also disclosed.

The present invention relates to a neuromimetic network comprising a set of neurons and a set of synapses, at least one neuron comprising a first stack of superimposed layers, the first stack successively comprising: a first electrode, a first barrier layer made of an electrically insulating material, and a second electrode, the first electrode, the first barrier layer and the second electrode forming a first ferroelectric tunnel junction, at least one synapse comprising a second stack of superimposed layers, the second stack successively comprising: a third electrode, a second barrier layer made of an electrically insulating material, and a fourth electrode, the third electrode, the second barrier layer and the fourth electrode forming a second ferroelectric tunnel junction.

A device includes plural semiconductor fins, a gate structure, an interlayer dielectric (ILD) layer, and an isolation dielectric. The gate structure is across the semiconductor fins. The ILD surrounds the gate structure. The isolation dielectric is at least between the semiconductor fins and has a thermal conductivity greater than a thermal conductivity of the ILD layer.