A stacked III-V semiconductor photonic device having a second metallic terminal contact layer at least formed in regions, a highly doped first semiconductor contact region of a first conductivity type, a very low doped absorption region of the first or second conductivity type having a layer thickness of 20 μm-2000 μm, a first metallic terminal contact layer, wherein the first semiconductor contact region extends into the absorption region in a trough shape, the second metallic terminal contact layer is integrally bonded to the first semiconductor contact region and the first metallic terminal contact layer is arranged below the absorption region. In addition, the stacked III-V semiconductor photonic device has a doped III-V semiconductor passivation layer of the first or second conductivity type, wherein the III-V semiconductor passivation layer is arranged at a first distance of at least 10 μm to the first semiconductor contact region.

Fabricating a regrown GaN p-n junction includes depositing a n-GaN layer on a substrate including n.sup.+-GaN, etching a surface of the n-GaN layer to yield an etched surface, depositing a p-GaN layer on the etched surface, etching a portion of the n-GaN layer and a portion of the p-GaN layer to yield a mesa opposite the substrate, and passivating a portion of the p-GaN layer around an edge of the mesa. The regrown GaN p-n junction is defined at an interface between the n-GaN layer and the p-GaN layer. The regrown GaN p-n junction includes a substrate, a n-GaN layer on the substrate having an etched surface, a p-GaN layer on the etched surface, a mesa defined by an etched portion of the n-GaN layer and an etched portion of the p-GaN layer, and a passivated portion of the p-GaN layer around an edge of the mesa.

A semiconductor structure is provided. The semiconductor structure includes a substrate, a diode region, and a dummy stripe. The substrate has a first surface. The diode region is in the substrate. The diode region includes a first implant region of a first conductivity type approximate to the first surface, and a second implant region of a second conductivity type approximate to the first surface and surrounded by the first implant region. The dummy stripe is on the first surface and located between the first implant region and the second implant region. A method for manufacturing a semiconductor structure is also provided.

A high voltage edge termination structure for a power semiconductor device is provided. The high voltage edge termination structure comprises a semiconductor body of a first conductive type, a JTE region of a second conductive type, a heavily doped channel stop region of the first conductive type, and a plurality of field plates. The JTE region is formed in the semiconductor body, wherein the JTE region is adjacent to an active region of the power semiconductor device. The heavily doped channel stop region is formed in the semiconductor body, wherein the heavily doped channel stop region is spaced apart from the JTE region. The plurality of field plates is formed on the JTE region.

According to one embodiment, a wafer includes a base body including a first surface, and a crystal layer provided on the first surface. The crystal layer includes first stacking faults and one or second stacking faults. One of the first stacking faults includes a first long side, a first short side, and a first hypotenuse. A position of the first long side in a first direction from the base body to the crystal layer is between the base body in the first direction and a first corner portion in the first direction. One of the one or the plurality of second stacking faults includes a second long side, a second short side, and a second hypotenuse. A position of a second corner portion in the first direction is between the base body in the first direction and the second long side in the first direction.

An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.

A Freewheeling Diode of any kind (Fast Recovery Diode, Schottky Barrier Diode or other variants) is integrated with a Forced Extraction Device and in this way two entirely different functions—the Free-Wheeling function and the Forced Extraction function are combined in one device, simplifying the circuit and reducing the number of components. The FWD part of the integrated device is standard in the industry, but the Forced Extraction Device is made using a lateral or vertical PMOS with a votage capability between a control input and the output terminals that is as high or higher than the rating voltage of the Main Switch that will be used together with the FWD.

A p-type semiconductor region is formed in a front surface side of an n-type semiconductor substrate. An n-type field stop (FS) region including protons as a donor is formed in a rear surface side of the semiconductor substrate. A concentration distribution of the donors in the FS region include first, second, third and fourth peaks in order from a front surface to the rear surface. Each of the peaks has a peak maximum point, and peak end points formed at both sides of the peak maximum point. The peak maximum points of the first and second peaks are higher than the peak maximum point of the third peak. The peak maximum point of the third peak is lower than the peak maximum point of the fourth peak.

A semiconductor device has a silicon film for a diode formed on a semiconductor substrate via an insulating film, and first and second wirings formed on an upper layer of the silicon film. The silicon film has a p-type silicon region and a plurality of n-type silicon regions, and each of the plurality of n-type silicon regions is surrounded by the p-type silicon region in a plan view. The p-type silicon region is electrically connected to the first wiring, and the plurality of n-type silicon regions are electrically connected to the second wiring.

A semiconductor device includes first and second insulating films and a semiconductor part. The semiconductor part is provided on the first insulating film and surrounded by the second insulating film. The semiconductor part includes first and fourth semiconductor layers of a first conductivity type, second and third semiconductor layers of a second conductivity type, and first to third contact regions provided respectively on the second to fourth semiconductor layer. The second to fourth semiconductor layers are arranged in a first direction on the first semiconductor layer. The fourth semiconductor layer is provided between the second and third semiconductor layers. The first and second contact regions being provided with first distances to the second insulating film in a second direction crossing the first direction. The first distances are less than a second distance in the second direction from the third contact region to the second insulating film.