A semiconductor substrate includes a base portion, an auxiliary layer and a surface layer. The auxiliary layer is formed on the base portion. The surface layer is formed on the auxiliary layer. The surface layer is in contact with a first main surface of the semiconductor substrate. The auxiliary layer has a different electrochemical dissolution efficiency than the base portion and the surface layer. At least a portion of the auxiliary layer and at least a portion of the surface layer are converted into a porous structure. Subsequently, an epitaxial layer is formed on the first main surface.

An integrated circuit includes a shallow P-type well (SPW) below a surface of a semiconductor substrate and a shallow N-type well (SNW) below the surface. The SPW forms an anode of a diode and the SNW forms a cathode of the diode. The SNW is spaced apart from the SPW by a well space region; and a thin field relief oxide structure lies over the well space region.

The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.

An edge delimits a semiconductor body in a direction parallel to a first side of the semiconductor body. A peripheral area is arranged between the active area and edge. A first semiconductor region of a first conductivity type extends from the active area into the peripheral area. A second semiconductor region of a second conductivity type forms a pn-junction with the first semiconductor region. A first edge termination region of the second conductivity type arranged at the first side adjoins the first semiconductor region, between the second semiconductor region and edge. A second edge termination region of the first conductivity type arranged at the first side and between the first edge termination region and edge has a varying concentration of dopants of the first conductivity type which increases at least next to the first edge termination region substantially linearly with an increasing distance from the first edge termination region.

A fast recovery diode includes a cell region, a main junction region arranged around the cell region, and a termination region arranged around the main junction region. A main junction doping region in the main junction region has a doping concentration lower than that of an active region in the cell region. The doping concentration of the main junction doping region gradually decreases along a direction from inside to outside.

Aspects for forming a self-aligned single diffusion break (SDB) isolation structure in a gate region of a diode for reduced capacitance, resistance, and/or area are disclosed. In one aspect, a diode is provided that includes a semiconductor substrate having a well region. P-doped and N-doped diffusion regions are formed in the well region of the semiconductor substrate. A self-aligned SDB isolation structure is formed in and self-aligned with a gate region between the P-doped and N-doped diffusion regions that electrically isolates such regions. The self-aligned SDB isolation structure reduces the parasitic capacitance of the diode compared to diodes having conductive gate structures in the gate region. The self-aligned SDB isolation structure has a width that reduces the length of a discharge path compared to conventional diodes, which reduces on-state resistance of the diode.

According to various embodiments, a method for processing an electronic component including at least one electrically conductive contact region may include: forming a contact pad including a self-segregating composition over the at least one electrically conductive contact region to electrically contact the electronic component; forming a segregation suppression structure between the contact pad and the electronic component, wherein the segregation suppression structure includes more nucleation inducing topography features than the at least one electrically conductive contact region for perturbing a chemical segregation of the self-segregating composition by crystallographic interfaces of the contact pad defined by the nucleation inducing topography features.

An electric assembly includes a reverse conducting switching device and a rectifying device. The reverse conducting switching device includes transistor cells for desaturation configured to be, under reverse bias, turned on in a desaturation mode and to be turned off in a saturation mode. The rectifying device is electrically connected anti-parallel to the switching device. In a range of a diode forward current from half of a maximum rating diode current of the switching device to the maximum rating diode current, a diode I/V characteristic of the rectifying device shows a voltage drop across the rectifying device higher than a saturation I/V characteristic of the switching device with the transistor cells for desaturation turned off and lower than a desaturation I/V characteristic of the switching device with the transistor cells for desaturation turned on.

The semiconductor device of the present invention includes a semiconductor substrate, a switching element which is defined on the semiconductor substrate, and a temperature sense element which is provided on the surface of the semiconductor substrate independently from the switching element and characterized by being dependent on a temperature.

A power semiconductor device includes a wiring structure adjoining at least one side of a semiconductor body and comprising at least one electrically conductive compound. The power semiconductor device further includes a cooling material in the wiring structure. The cooling material is characterized by a change in structure by means of absorption of energy at a temperature T.sub.C ranging between 150° C. and 400° C.