The present description concerns a method of forming a cavity in a substrate comprising: the forming of an etch mask comprising, opposite the location of the cavity, a plurality of sets of openings, the ratio between the openings and the mask of each set being selected according to the desired profile of the cavity opposite the surface of the mask having the set inscribed therein; and the wet etching of the substrate through the openings.

In a semiconductor device according to the technology disclosed in the present specification, a temperature detection region is provided with a diffusion layer of a second conductivity type provided on a surface layer of a drift layer of a first conductivity type, a well layer of a first conductivity type provided on a surface layer of the diffusion layer and electrically connected to an anode electrode, and a cathode layer of a first conductivity type provided on a surface layer of the well layer and electrically connected to a cathode electrode.

A semiconductor device includes a semiconductor substrate, a contact region, a carrier suppression region and an electrode. The semiconductor substrate is shared by an insulated gate bipolar transistor (IGBT) region with an IGBT element and a freewheeling diode (FWD) region with an FWD element. The carrier suppression region is exposed from a surface of the semiconductor substrate in the IGBT region, and has a lower impurity concentration than the contact region. The carrier suppression region has a Schottky barrier junction with the electrode.

A power device includes: a diode section; a semiconductor body; a drift region extending into the diode section; trenches in the diode section and extending along a vertical direction into the semiconductor body, two adjacent trenches defining a respective mesa portion in the semiconductor body; a body region in the mesa portions; in the diode section, a barrier region between the body and drift regions and having a dopant concentration at least 100 times greater than an average dopant concentration of the drift region and a dopant dose greater than that of the body region. The barrier region has a lateral structure according to which at least 50% of the body region in the diode section is coupled to the drift region at least by the barrier region, and at least 5% of the body region in the diode section is coupled to the drift region without the barrier region.

Provided is a semiconductor device that includes a semiconductor substrate that is provided with a first conductivity type drift region, a transistor portion that includes a second conductivity type collector region in contact with a lower surface of the semiconductor substrate, and a diode portion that includes a first conductivity type cathode region in contact with the lower surface of the semiconductor substrate, and is alternately disposed with the transistor portion along an arrangement direction in an upper surface of the semiconductor substrate. In the transistor portions, a width in the arrangement direction of two or more transistor portions sequentially selected from the transistor portions nearer to the center in the arrangement direction of the semiconductor substrate is larger than a width in the arrangement direction of one of the other transistor portions.

A semiconductor device includes a semiconductor substrate, an emitter region, a base region and multiple accumulation areas, and an upper accumulation area in the multiple accumulation areas is in direct contact with a gate trench section and a dummy trench section, in an arrangement direction that is orthogonal to a depth direction and an extending direction, a lower accumulation area furthest from the upper surface of the semiconductor substrate in the multiple accumulation areas has: a gate vicinity area closer to the gate trench section than the dummy trench section in the arrangement direction; and a dummy vicinity area closer to the dummy trench section than the gate trench section in the arrangement direction, and having a doping concentration of the first conductivity type lower than that of the gate vicinity area.

A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

An RC IGBT includes: an active region with separate IGBT and diode sections; a semiconductor body forming a part of the active region; a first load terminal and control terminal at a first side of the body and a second load terminal at a second side, the control terminal including a control terminal finger that laterally overlaps, in the active region, with the diode section. Control trenches extending into the semiconductor body along a vertical direction have a control trench electrode electrically connected to the control terminal for controlling a load current between the load terminals in the IGBT section. At least one control trench extends into both IGBT and diode sections. The electrical connection between the control trench electrode of that control trench and the control terminal is established at least based on an electrically conductive member arranged, in the diode section, in contact with the control terminal finger.

A semiconductor device is proposed. The semiconductor device includes a semiconductor substrate including a RC-IGBT with a diode area. The diode area includes a p-doped anode region and an n-doped emitter efficiency adjustment region. At least one of the p-doped anode region or the n-doped emitter efficiency adjustment region includes deep level dopants.

Plural sessions of proton irradiation are performed by differing ranges from a substrate rear surface side. After first to fourth n-type layers of differing depths are formed, the protons are activated. Next, helium is irradiated to a position deeper than the ranges of the proton irradiation from the substrate rear surface, introducing lattice defects. When the amount of lattice defects is adjusted by heat treatment, protons not activated in a fourth n-type layer are diffused, forming a fifth n-type layer contacting an anode side of the fourth n-type layer and having a carrier concentration distribution that decreases toward the anode side by a more gradual slope than that of the fourth n-type layer. The fifth n-type layer that includes protons and helium and the first to fourth n-type layers that include protons constitute an n-type FS layer. Thus, a semiconductor device having improved reliability and lower cost may be provided.