Provided is a semiconductor device including a drift region, a base region, two trench portions and a mesa portion, wherein at least one of the two trench portions is a gate trench portion, the mesa portion includes: a first conductivity type emitter region provided to be exposed on an upper surface of the mesa portion; a second conductivity type contact region provided to be exposed on the upper surface of the mesa portion alternately with the emitter region in an extending direction; and a second conductivity type connecting region with a higher doping concentration than the base region, wherein the connecting region is provided to overlap with the emitter region in a top view, is arranged apart from the gate trench portion, is arranged below the upper surface of the mesa portion, and connects two of the contact regions sandwiching the emitter region in the extending direction.

A semiconductor device includes: a first electrode; a first semiconductor layer on the first electrode in a diode region; a second semiconductor layer on the first electrode in an IGBT region; a semiconductor layer on the first and second semiconductor layers, a first upper layer of the semiconductor layer in the diode region including a first region adjacent to the IGBT region and a second region separated from the IGBT region, an impurity concentration being less in the first region than in the second region; a third semiconductor layer on the semiconductor layer; a fourth semiconductor layer of the third semiconductor layer in the IGBT region; a third electrode extending in a direction from the fourth semiconductor layer toward the semiconductor layer; and an insulating film between the second electrode and each of the third semiconductor layer, the semiconductor layer, and the third electrode.

Process flow for a stacked power diode and design of the resulting diode is disclosed. Blanket epitaxy over heavy doped wafers is performed. By controlling dopant addition during epitaxy, desired n-type, diode base, and p-type doping profiles and thicknesses achieved. V-groove pattern if formed on wafers by depositing mask film, lithography and anisotropic etch. Islands surrounded by V-grooves define individual diodes. V-grooves serve as side insulation. Next, oxidation step passivates V-grooves. Further, the mask film is stripped to open diode contact areas on both sides of wafers. Next high melting point metal and low melting point metal films are selectively electroplated on all open silicon surfaces. Stacking is performed on wafer level by bonding of desired wafer count by solid-liquid interdiffusion process. Wafer stacks are sawed into individual stacked diode dies along outer slopes of V-grooves. Final stacked devices can be used as DSRD—drift step recovery diodes. Compared to DSRDs made by known methods, better fabrication yield and higher pulse power electrical performance is achieved.

A semiconductor device includes: a first electrode; a first semiconductor layer of first conductivity type provided on the first electrode; a second semiconductor layer of second conductivity type provided on the first semiconductor layer; a second electrode provided on the second semiconductor layer; a first trench reaching the first semiconductor layer from the second semiconductor layer; a first semiconductor region provided in the second semiconductor layer, the first semiconductor region being in contact with the first trench and the first semiconductor region having a higher concentration of impurities of second conductivity type than the second semiconductor layer; and a first insulating film provided in the second semiconductor layer and the first insulating film being in contact with the first semiconductor region.

A semiconductor device includes: a first semiconductor layer located in a diode region, the first semiconductor layer including a plurality of first semiconductor regions and a plurality of second semiconductor regions alternately arranged in a first direction; a second semiconductor layer located in the IGBT region; and a third semiconductor layer located on the first semiconductor layer in the diode region, an impurity concentration of the third semiconductor layer having a maximum at a first position in a second direction, an impurity concentration of the first semiconductor region having a maximum at a second position in the second direction, a third position being separated from the upper surface of the first electrode by a length that is 3 times a distance between the second position and a lower end of the third semiconductor layer, the first position being the same as or lower than the third position.

A method for manufacturing an optical device includes providing a carrier waver, provide a first substrate having a first surface region, and forming a first gallium and nitrogen containing epitaxial material overlying the first surface region. The first epitaxial material includes a first release material overlying the first substrate. The method also includes patterning the first epitaxial material to form a plurality of first dice arranged in an array; forming a first interface region overlying the first epitaxial material; bonding the first interface region of at least a fraction of the plurality of first dice to the carrier wafer to form bonded structures; releasing the bonded structures to transfer a first plurality of dice to the carrier wafer, the first plurality of dice transferred to the carrier wafer forming mesa regions on the carrier wafer; and forming an optical waveguide in each of the mesa regions, the optical waveguide configured as a cavity to form a laser diode of the electromagnetic radiation.

A diode region includes: an n-type first semiconductor layer provided on a second-main-surface side in the semiconductor substrate; an n-type second semiconductor layer provided on the first semiconductor layer; a p-type third semiconductor layer provided closer to a first main surface of the semiconductor substrate than the second semiconductor layer; a first main electrode that applies a first potential to the diode; a second main electrode that applies a second potential to the diode; and a dummy active trench gate provided so as to extend from the first main surface of the semiconductor substrate and reach the second semiconductor layer. The dummy active trench gate includes the third semiconductor layer that is not applied with the first potential to be in a floating state on at least one of two side surfaces, and the dummy active trench gate is applied with a gate potential of the transistor.

Provided is a semiconductor device including a semiconductor substrate having a first dopant of a first conductivity type and a second dopant of a second conductivity type, both the first dopant and the second dopant being distributed in an entire part of the semiconductor substrate, the semiconductor substrate including a drift region of the first conductivity type, a dielectric film provided on an upper surface of the semiconductor substrate, a high concentration region of the first conductivity type provided in contact with the dielectric film below the dielectric film and having a higher doping concentration than the drift region, and a fall off region that is provided in contact with the dielectric film below the dielectric film and in which a concentration of the dopant of the second conductivity type decreases toward the dielectric film.

Systems and methods for building passive and active electronics with diamond-like carbon (DLC) coatings are provided herein. DLC may be layered upon substrates to form various components of electronic devices. Passive components such as resistors, capacitors, and inductors may be built using DLC as a dielectric or as an insulating layer. Active components such as diodes and transistors may be built with the DLC acting substantially like a semiconductor. The amount of sp.sup.2 and sp.sup.3 bonded carbon atoms may be varied to modify the properties of the DLC for various electronic components.

Provided is a manufacturing method for a semiconductor device including forming a first electrode layer on a front surface of a wafer, implanting, into an outer peripheral region of the front surface of the wafer, a heavy ion of an element in third and subsequent rows of a periodic table, forming an oxide film in the outer peripheral region into which the heavy ion has been implanted, and forming a second electrode layer on the first electrode layer by plating. A dose of the heavy ion may be 1E15 cm.sup.−2 or more. A depth of an implantation range of the heavy ion into the wafer may be 0.02 μm or more. The heavy ion may be an As ion, a P ion, or an Ar ion.