The present disclosure relates to a non-volatile ferroelectric memory and a method of preparing the same. The ferroelectric memory includes a ferroelectric storage layer, a first electrode and a second electrode; the first electrode and the second electrode each include a buried conductive layer formed by patterning in a surface of the ferroelectric storage layer and an electrode layer formed on the buried conductive layer; and when a write signal in a certain direction is applied between the first electrode and the second electrode, the electric domains of a part of the ferroelectric storage layer between a pair of the buried conductive layers are enabled to be reversed, so that a domain wall conductive passage that electrically connects the first electrode and the second electrode can be established.

A resistive memory device including a first electrode and a second electrode facing each other and a variable resistance layer disposed between the first electrode and the second electrode, wherein the variable resistance layer includes Cd-free quantum dots (Cd-free quantum dots) and at least a portion of the Cd-free quantum dots include a Cd-free quantum dot including a halide anion on a surface of the Cd-free quantum dot, a method of manufacturing the same and an electronic device.

A two-terminal biristor in which a polysilicon emitter layer is inserted and a method of manufacturing the same are provided. The method of manufacturing the two-terminal biristor according to an embodiment of the present disclosure includes forming a first semiconductor layer of a first type on a substrate, forming a second semiconductor layer of a second type on the first semiconductor layer, forming a third semiconductor layer of the first type on the second semiconductor layer, and forming a polysilicon layer of the first type on the third semiconductor layer.

A diode is formed by a polycrystalline silicon bar which includes a first doped region with a first conductivity type, a second doped region with a second conductivity type and an intrinsic region between the first and second doped regions. A conductive layer extends parallel to the polycrystalline silicon bar and separated from the polycrystalline silicon bar by a dielectric layer. The conductive layer is configured to be biased by a bias voltage.

A switching device including a GaN substrate; an unintentionally doped GaN layer on a first surface of the GaN substrate; a regrown unintentionally doped GaN layer on the unintentionally doped GaN layer; a regrowth interface between the unintentionally doped GaN layer and the regrown unintentionally doped GaN layer; a p-GaN layer on the regrown unintentionally doped GaN layer; a first electrode on the p-GaN layer; and a second electrode on a second surface of the GaN substrate.

A semiconductor storage device comprises a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a semiconductor storage element including a silicon carbide substrate and a silicon carbide film on a first surface of the silicon carbide substrate; a lower electrode on a second surface facing away from the first surface of the silicon carbide substrate; and an upper electrode on at least part of a surface of the silicon carbide film, the surface facing away from another surface of the silicon carbide film in contact with the silicon carbide substrate. Each memory cell includes at least one basal plane dislocation formed at at least part of the semiconductor storage element.

A threshold switching device is provided. The threshold switching device includes a first electrode and a second electrode spaced apart from each other, and a switching layer disposed between the first electrode and the second electrode. The switching layer includes an internal electric field.

A two-terminal memory device includes: a substrate; an extended drain extending from a drain and a lower surface of the drain and laminated on the substrate; a ferroelectric layer connected to the drain and covering the extended drain and the substrate; and a source laminated on the ferroelectric layer to face the drain.

A method for manufacturing a two-terminal memory device includes: forming an extended drain and a drain layer on a substrate; forming a ferroelectric layer covering the substrate and the extended drain; forming a semiconducting layer on the ferroelectric layer, and forming a source layer connected to the semiconducting layer on the ferroelectric layer.

A resistive memory element includes a P-type layer, a tunneling structure and an N-type layer. The tunneling structure is formed on the P-type layer. The N-type layer is formed on the tunneling structure. When a bias voltage higher than a reset voltage is applied to the P-type layer and the N-type layer, the resistive memory element is in a reset state. When the bias voltage lower than a set voltage is applied to the P-type layer and the N-type layer, the resistive memory element is in a set state.