A low dynamic resistance, low capacitance diode of a semiconductor device includes a heavily-doped n-type substrate. A lightly-doped n-type layer 1 micron to 5 microns thick is disposed on the n-type substrate. A lightly-doped p-type layer 3 microns to 8 microns thick is disposed on the n-type layer. The low dynamic resistance, low capacitance diode, of the semiconductor device includes a p-type buried layer, with a peak dopant density above 110.sup.17 cm.sup.3, extending from the p-type layer through the n-type layer to the n-type substrate. The low dynamic resistance, low capacitance diode also includes an n-type region disposed in the p-type layer, extending to a top surface of the p-type layer.

To reduce defects in an oxide semiconductor film in a semiconductor device. To improve electrical characteristics of and reliability in the semiconductor device including an oxide semiconductor film. A method for manufacturing a semiconductor device includes the steps of forming a gate electrode and a gate insulating film over a substrate, forming an oxide semiconductor film over the gate insulating film, forming a pair of electrodes over the oxide semiconductor film, forming a first oxide insulating film over the oxide semiconductor film and the pair of electrodes by a plasma CVD method in which a film formation temperature is 280? C. or higher and 400? C. or lower, forming a second oxide insulating film over the first oxide insulating film, and performing heat treatment at a temperature of 150? C. to 400? C. inclusive, preferably 300? C. to 400? C. inclusive, further preferably 320? C. to 370? C. inclusive.

A light emitting diode (LED) to emit ultraviolet (UV) light includes a first n-type semiconductor region and a first p-type semiconductor region. The LED also includes an active region disposed between the first n-type semiconductor region and the first p-type semiconductor region, and in response to a bias applied across the light emitting diode, the active region emits UV light. A tunnel junction is disposed in the LED so the first p-type semiconductor region is disposed between the active region and the tunnel junction. The tunnel junction is electrically coupled to inject charge carriers into the active region through the first p-type semiconductor region. A second n-type semiconductor region is also disposed in the LED so the tunnel junction is disposed between the second n-type semiconductor region and the first p-type semiconductor region.

To reduce defects in an oxide semiconductor film in a semiconductor device. To improve electrical characteristics of and reliability in the semiconductor device including an oxide semiconductor film. A method for manufacturing a semiconductor device includes the steps of forming a gate electrode and a gate insulating film over a substrate, forming an oxide semiconductor film over the gate insulating film, forming a pair of electrodes over the oxide semiconductor film, forming a first oxide insulating film over the oxide semiconductor film and the pair of electrodes by a plasma CVD method in which a film formation temperature is 280? C. or higher and 400? C. or lower, forming a second oxide insulating film over the first oxide insulating film, and performing heat treatment at a temperature of 150? C. to 400? C. inclusive, preferably 300? C. to 400? C. inclusive, further preferably 320? C. to 370? C. inclusive.

A semiconductor device includes a first diode having a cathode connected to a first terminal, a second diode having a cathode connected to a second terminal and an anode connected to an anode of the first diode, a third diode having an anode connected to the first terminal and the cathode of the first diode, a fourth diode having an anode connected to the second terminal and the anode of the second diode and a cathode connected to a cathode of the third diode, and a fifth diode having an anode connected to the anode of the first diode and the anode of the second diode and a cathode connected to the cathode of the third diode and the fourth diode. A breakdown voltage of the fifth diode is lower than the breakdown voltages of the first diode, the second diode, the third diode, and the fourth diode.

Provided are a diode, a junction field effect transistor (JFET), and a semiconductor device that have a top doped region. A dopant concentration gradient of the top doped region at one side is different from the dopant concentration gradient of the top doped region at an opposite side. The top doped region is able to increase a breakdown voltage of the device and decrease an on-state resistance (Ron) of the device.

An electrostatic discharge circuit may include a substrate, an N+ buried layer in the substrate, an n-type epitaxial layer on the N+ buried layer and the substrate, a first P region in an anode region of the n-type epitaxial layer, a first N+ region in the first P region, an N-well in a cathode region of the n-type epitaxial layer, a first P+ region in the N-well, and a second N+ region located in the N-well. The first N+ region may be located closer to the second N+ region than the first P+ region.

Provided are a diode, a junction field effect transistor (JFET), and a semiconductor device that have a top doped region. A dopant concentration gradient of the top doped region at one side is different from the dopant concentration gradient of the top doped region at an opposite side. The top doped region is able to increase a breakdown voltage of the device and decrease an on-state resistance (Ron) of the device.

A method for making a semiconductor device may include forming at least one a double-barrier resonant tunneling diode (DBRTD) by forming a first doped semiconductor layer, and a forming first barrier layer on the first doped semiconductor layer and including a superlattice. The method may further include forming a first intrinsic semiconductor layer on the first barrier layer, forming a second barrier layer on the first intrinsic semiconductor layer and also comprising the superlattice, forming a second intrinsic semiconductor layer on the second barrier layer, and forming a third barrier layer on the second intrinsic semiconductor layer and also comprising the superlattice. The method may further include forming a third intrinsic semiconductor layer on the third barrier layer, forming a fourth barrier layer on the third intrinsic semiconductor layer, and forming a second doped semiconductor layer on the fourth barrier layer.

A semiconductor device may include at least one double-barrier resonant tunneling diode (DBRTD). The at least one DBRTD may include a first doped semiconductor layer and a first barrier layer on the first doped semiconductor layer and including a superlattice. The superlattice may include stacked groups of layers, each group of layers including a plurality of stacked base semiconductor monolayers defining a base semiconductor portion, and at least one non-semiconductor monolayer constrained within a crystal lattice of adjacent base semiconductor portions. The at least one DBRTD may further include an intrinsic semiconductor layer on the first barrier layer, a second barrier layer on the intrinsic semiconductor layer, and a second doped semiconductor layer on the second superlattice layer.