A method of manufacturing a light emitting device that comprises a first cover member and a second cover member, includes: providing a package that comprises a substrate, a plurality of resin walls, and a recessed part defined by an upper surface of the substrate and lateral surfaces of the plurality of resin walls, wherein the substrate includes a grooved part surrounding a first region; mounting a light emitting element in the first region; forming the second cover member in a region between the lateral surfaces defining the recessed part to an upper edge of an outer perimeter of the grooved part; forming the first cover member, which comprises depositing an uncured resin on the second cover member, and allowing the uncured resin to flow into a groove of the grooved part; and forming a light transmitting member on the first cover member and the light emitting element.

A method of manufacturing a light emitting device that comprises a first cover member and a second cover member, includes: providing a package that comprises a substrate, a plurality of resin walls, and a recessed part defined by an upper surface of the substrate and lateral surfaces of the plurality of resin walls, wherein the substrate includes a grooved part surrounding a first region; mounting a light emitting element in the first region; forming the second cover member in a region between the lateral surfaces defining the recessed part to an upper edge of an outer perimeter of the grooved part; forming the first cover member, which comprises depositing an uncured resin on the second cover member, and allowing the uncured resin to flow into a groove of the grooved part; and forming a light transmitting member on the first cover member and the light emitting element.

For example, a semiconductor device includes an output electrode to be connected to an inductive load, a ground electrode to be connected to a ground terminal, first and second transistors connected in parallel between the output and ground electrodes, an active clamp circuit connected to the gate of the first transistor, and a gate control circuit to control the gates of the first and second transistors to keep the first and second transistors on in a first operation state and off in a second operation state. After a transition from the first operation state to the second, before the active clamp circuit operates, the gate control circuit short-circuits between the gate and source of the second transistor.

For example, a semiconductor device includes an output electrode to be connected to an inductive load, a ground electrode to be connected to a ground terminal, first and second transistors connected in parallel between the output and ground electrodes, an active clamp circuit connected to the gate of the first transistor, and a gate control circuit to control the gates of the first and second transistors to keep the first and second transistors on in a first operation state and off in a second operation state. After a transition from the first operation state to the second, before the active clamp circuit operates, the gate control circuit short-circuits between the gate and source of the second transistor.

A semiconductor device includes a semiconductor substrate having a major surface and both an element-forming region and an outer peripheral voltage-withstanding region that are provided on the major surface side of the semiconductor substrate. The element-forming region includes both a cell region for forming a power element and a circuit element region for forming at least one circuit element. The circuit element region is interposed between the outer peripheral voltage-withstanding region and the cell region. The outer peripheral voltage-withstanding region includes a boundary region that adjoins the element-forming region. In the boundary region, there is provided one or more voltage-withstanding regions. At least one of the one or more voltage-withstanding regions has a withstand voltage lower than both the withstand voltages of the cell region and the circuit element region.

A semiconductor power device having shielded gate structure in an active area and trench field plate termination surrounding the active area is disclosed. A Zener diode connected between drain metal and source metal or gate metal for functioning as a SD or GD clamp diode. Trench field plate termination surrounding active area wherein only cell array located will not cause BV degradation when SD or GD poly clamped diode integrated.

A semiconductor power device having shielded gate structure in an active area and trench field plate termination surrounding the active area is disclosed. A Zener diode connected between drain metal and source metal or gate metal for functioning as a SD or GD clamp diode. Trench field plate termination surrounding active area wherein only cell array located will not cause BV degradation when SD or GD poly clamped diode integrated.

A transient voltage suppressor is disclosed that includes an electrode, a substrate disposed on the electrode, the substrate having a first doping, an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping that is different from the first doping, a channel formed in the epitaxial layer having a width W, a length L and a plurality of curved regions, the channel forming a plurality of adjacent sections, the channel having a third doping that is different from the first doping and the second doping and a metal layer formed on top of the channel and contained within the width W of the channel.

A transient voltage suppressor is disclosed that includes an electrode, a substrate disposed on the electrode, the substrate having a first doping, an epitaxial layer disposed on the substrate, the epitaxial layer having a second doping that is different from the first doping, a channel formed in the epitaxial layer having a width W, a length L and a plurality of curved regions, the channel forming a plurality of adjacent sections, the channel having a third doping that is different from the first doping and the second doping and a metal layer formed on top of the channel and contained within the width W of the channel.

A transient voltage suppression device includes: a substrate; a first conductive type well region including a first well and a second well; a second conductive type well region including a third well and a fourth well, the third well being disposed between the first well and the second well so as to isolate the first well and the second well, and the second well being disposed between the third well and the fourth well; a zener diode active region; a first doped region, provided in the first well; a second doped region, provided in the first well; a third doped region, provided in the second well; a fourth doped region, provided in the second well; a fifth doped region, provided in the zener diode active region; and a sixth doped region, provided in the zener diode active region.