Disclosed are a diode and a manufacturing method thereof. The diode includes: a first substrate, the first substrate being an N-type doped substrate with a doping concentration equal to or greater than 1×10.sup.18 cm.sup.−3; a metal atomic layer located on a first surface of the first substrate; an epitaxial structure located on the metal atomic layer; a first electrode located on the epitaxial structure; and a second electrode located on a second surface, opposite to the first surface, of the first substrate. The diode significantly reduces forward conduction voltage drop.

Techniques are provided herein to form a semiconductor diode device within an integrated circuit. In an example, a diode device includes separate fins or bodies of semiconductor material that are separated by an insulating barrier. One of the fins or bodies is doped with n-type dopants while the other fin or body is doped with p-type dopants. Each of the first and second fins or bodies includes an epitaxially grown region over it that includes the corresponding dopant type with a higher dopant concentration. Additionally, each of the first and second fins or bodies includes another epitaxially grown region on the backside (e.g., under the fins or bodies) of the corresponding dopant type with a lower dopant concentration compared to the epitaxial regions on the opposite side of the fins or bodies. An undoped or lightly doped layer may also be formed between the epitaxially grown regions on the backside.

Techniques are provided herein to form a semiconductor diode device within an integrated circuit. In an example, a diode device includes separate fins or bodies of semiconductor material that are separated by an insulating barrier. One of the fins or bodies is doped with n-type dopants while the other fin or body is doped with p-type dopants. Each of the first and second fins or bodies includes an epitaxially grown region over it that includes the corresponding dopant type with a higher dopant concentration. Additionally, each of the first and second fins or bodies includes another epitaxially grown region on the backside (e.g., under the fins or bodies) of the corresponding dopant type with a lower dopant concentration compared to the epitaxial regions on the opposite side of the fins or bodies. An undoped or lightly doped layer may also be formed between the epitaxially grown regions on the backside.

The present invention relates to a vertical semiconductor device such as an IGBT or a diode which includes an N buffer layer formed in the undersurface of and adjacent to an N.sup.− drift layer. A concentration slope δ, which is derived from displacements in a depth TB (μm) and an impurity concentration CB (cm.sup.−3), from the upper surface to the lower surface in a main portion of the N buffer layer satisfies a concentration slope condition defined by {0.03≦δ≦0.7}.

The present invention relates to a vertical semiconductor device such as an IGBT or a diode which includes an N buffer layer formed in the undersurface of and adjacent to an N.sup.− drift layer. A concentration slope δ, which is derived from displacements in a depth TB (μm) and an impurity concentration CB (cm.sup.−3), from the upper surface to the lower surface in a main portion of the N buffer layer satisfies a concentration slope condition defined by {0.03≦δ≦0.7}.

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer.

Disclosed herein is a new and improved system and method for fabricating diamond semiconductors. The method may include the steps of selecting a diamond semiconductor material having a surface, exposing the surface to a source gas in an etching chamber, forming a carbide interface contact layer on the surface; and forming a metal layer on the interface layer.

A semiconductor device includes a semiconductor layer of a first conductivity type having a first main surface at one side and a second main surface at another side, a trench gate structure including a gate trench formed in the first main surface of the semiconductor layer, and a gate electrode embedded in the gate trench via a gate insulating layer, a trench source structure including a source trench formed deeper than the gate trench and across an interval from the gate trench in the first main surface of the semiconductor layer, a source electrode embedded in the source trench, and a deep well region of a second conductivity type formed in a region of the semiconductor layer along the source trench, a ratio of a depth of the trench source structure with respect to a depth of the trench gate structure being not less than 1.5 and not more than 4.0, a body region of the second conductivity type formed in a region of a surface layer portion of the first main surface of the semiconductor layer between the gate trench and the source trench, a source region of the first conductivity type formed in a surface layer portion of the body region, and a drain electrode connected to the second main surface of the semiconductor layer.

An example system includes a processing circuit coupled to a memory system and an interface coupled between the processing circuit and a device. The memory system includes a resistive memory array comprising multiple memory structures. Each memory structure comprises a resistive memory cell and is associated with a P-I-N diode. The processing circuit is to access the resistive memory array responsive to a signal received from the device via the interface.

A semiconductor device includes a first conductive type semiconductor layer which has a principal surface, a second conductive type well region which demarcates an active region and an outer region on the principal surface and is formed on a surface layer portion of the principal surface and includes a high concentration portion high in impurity concentration on the active region side and includes a low concentration portion lower in impurity concentration than the high concentration portion on the outer region side, and a second conductive type impurity region of the active region which is formed on a surface layer portion of the principal surface.