A semiconductor device includes a semiconductor layer of a first conductivity type that has a main surface and that includes a device region, a base region of a second conductivity type that is formed in a surface layer portion of the main surface at the device region, a source region of the first conductivity type that is formed in a surface layer portion of the base region at an interval inward from a peripheral portion of the base region and that defines a channel region with the semiconductor layer, a base contact region of the second conductivity type that is formed in a region different from the source region at the surface layer portion of the base region and that has an impurity concentration exceeding an impurity concentration of the base region, a well region of the first conductivity type that is formed in the surface layer portion of the main surface at an interval from the base region at the device region and that defines a drift region with the base region, a drain region of the first conductivity type that is formed in a surface layer portion of the well region, an impurity region of the second conductivity type that is formed in the surface layer portion of the well region and that is electrically connected to the drain region, and a gate structure that has a gate insulating film covering the channel region on the main surface and a gate electrode facing the channel region on the gate insulating film and electrically connected to the source region and the base contact region.

A transient voltage suppression device includes a P-type semiconductor layer, a first N-type well, a first N-type heavily-doped area, a first P-type heavily-doped area, a second P-type heavily-doped area, and a second N-type heavily-doped area. The first N-type well and the second N-type heavily-doped area are formed in the layer. The first P-type heavily-doped area is formed in the first N-type well. The first P-type heavily-doped area is spaced from the bottom of the first N-type well. The second P-type heavily-doped area is formed within the first N-type well and spaced from the sidewall of the first N-type well. The second P-type heavily-doped area is formed between the first P-type heavily-doped area and the second N-type heavily-doped area.

The electrostatic discharge protection apparatus includes a substrate, a first well having a first conductivity type and disposed in the substrate, a second well having a second conductivity type and disposed in the first well, a first doping region having the first conductivity type and disposed in the second well, a second doping region having the first conductivity type and disposed in the second well, a third doping region having the second conductivity type and disposed in the second well, and a fourth doping region having the first conductivity type and disposed in the substrate. The first conductivity type is different from the second conductivity type. The second well, the first well, the substrate and the fourth doping region form a silicon controlled rectifier. Electrostatic discharge current flowing into the first doping region flows to the fourth doping region through the silicon controlled rectifier.

An ESD protection structure formed within a semiconductor substrate of an integrated circuit device. The ESD protection structure comprises a thyristor structure being formed from a first P-doped section forming an anode of the thyristor structure, a first N-doped section forming a collector node of the thyristor structure, a second P-doped section, and a second N-doped section forming a cathode of the thyristor structure. A low-resistance coupling is provided between an upper surface region of the collector node of the thyristor structure and the anode of the thyristor structure.

The present disclosure relates to an electrostatic protection device including an SCR and a manufacturing method thereof. The electrostatic protection device includes a third N+ doped region across an N-type well region and a P-type well region, and a third P+ doped region adjacent to the third N+ doped region. Each of the third N+ doped region and the third P+ doped region has a high doping concentration. In a case that Zener breakdown occurs in a PN junction structure between the third N+ doped region and the third P+ doped region, the SCR is triggered to form a discharge current path. The present disclosure can reduce a trigger voltage of an electrostatic protection device including an SCR, and can provide electrostatic protection devices having different trigger voltages, with high stability and high robustness.

Transient suppression circuit arrangements are disclosed. In one implementation of a transient suppression circuit, at least one avalanche diode is coupled in series with a DIAC, a silicon diode for alternating current (SIDAC) device or SIDACtor.

The disclosure relates to a data transmission system (100) comprising a signal line (101) and a ground line (103). A first signal path (102) is provided between the signal line (101) and the ground line (103). The first signal path (102) comprises a Shockley diode (104) having a cathode (106) and an anode (108). The cathode (106) is connected to the ground line (103) and the anode (108) is connected to the signal line (101).

The disclosure relates to a data transmission system (100) comprising a signal line (101) and a ground line (103). A first signal path (102) is provided between the signal line (101) and the ground line (103). The first signal path (102) comprises a Shockley diode (104) having a cathode (106) and an anode (108). The cathode (106) is connected to the ground line (103) and the anode (108) is connected to the signal line (101).

A semiconductor device is provided that includes at least three regions. Each region includes a first-type layer doped with a first type of charge carriers and a second-type layer doped with a second type of charge carriers, and the first-type layer and the second-type layer are positioned laterally along each region. The first-type layer and the second-type layer have opposite polarity, and the first-type layer of a region is positioned substantially across the second-type layer of a neighboring region, and the second-type layer of a region is positioned substantially across the first-type layer of a neighboring region and each region includes a second-type well doped with the second type of charge carriers, and the second-type well is positioned around at least the first-type layer.

An ESD protection device includes a semiconductor body having an upper surface, a plurality of p-type wells that each extend from the upper surface into the semiconductor body, a plurality of n-type wells that each extend from the upper surface into the semiconductor body, first isolation regions comprising an electrical insulator that laterally surrounds the p-type wells and extends from the upper surface into the semiconductor body at least as deep as the p-type wells, and second isolation regions comprising an electrical insulator that laterally surrounds the n-type wells and extends from the upper surface into the semiconductor body at least as deep as the n-type wells, wherein the p-type wells and the n-type wells alternate with one another a first direction, and wherein an isolating area of the first isolation regions is greater than an isolating area of the second isolation regions.