Patent classifications
H01L29/872
Semiconductor device
According to an embodiment of the invention, a semiconductor device includes a base body that includes silicon carbide, a first semiconductor member that includes silicon carbide and is of a first conductivity type, and a second semiconductor member that includes silicon carbide and is of a second conductivity type. A first direction from the base body toward the first semiconductor member is along a [0001] direction of the base body. The second semiconductor member includes a first region, a second region, and a third region. The first semiconductor member includes a fourth region. A second direction from the first region toward the second region is along a [1-100] direction of the base body. The fourth region is between the first region and the second region in the second direction. A third direction from the fourth region toward the third region is along a [11-20] direction of the base body.
Semiconductor device
According to an embodiment of the invention, a semiconductor device includes a base body that includes silicon carbide, a first semiconductor member that includes silicon carbide and is of a first conductivity type, and a second semiconductor member that includes silicon carbide and is of a second conductivity type. A first direction from the base body toward the first semiconductor member is along a [0001] direction of the base body. The second semiconductor member includes a first region, a second region, and a third region. The first semiconductor member includes a fourth region. A second direction from the first region toward the second region is along a [1-100] direction of the base body. The fourth region is between the first region and the second region in the second direction. A third direction from the fourth region toward the third region is along a [11-20] direction of the base body.
Graded doping in power devices
Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 μm. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.
Graded doping in power devices
Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 μm. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.
CRYSTAL, SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE
A crystal that is useful for semiconductor element and a semiconductor element that has enhanced electrical properties are provided. A crystal, including: a corundum structured crystalline oxide, the crystalline oxide including gallium and/or indium, and the crystalline oxide further including a metal of Group 4 of the periodic table. The crystal is used to make a semiconductor element, and the obtained semiconductor element is used to make a semiconductor device such as a power card. Also, the semiconductor element and the semiconductor device are used to make a semiconductor system.
CRYSTAL, SEMICONDUCTOR ELEMENT AND SEMICONDUCTOR DEVICE
A crystal that is useful for semiconductor element and a semiconductor element that has enhanced electrical properties are provided. A crystal, including: a corundum structured crystalline oxide, the crystalline oxide including gallium and/or indium, and the crystalline oxide further including a metal of Group 4 of the periodic table. The crystal is used to make a semiconductor element, and the obtained semiconductor element is used to make a semiconductor device such as a power card. Also, the semiconductor element and the semiconductor device are used to make a semiconductor system.
LAMINATE, SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING LAMINATE
A laminate contains a crystal substrate; a middle layer formed on a main surface of the crystal substrate, the middle layer comprising a mixture of an amorphous region in an amorphous phase and a crystal region in a crystal phase having a corundum structure mainly made of a first metal oxide; and a crystal layer formed on the middle layer and having a corundum structure mainly made of a second metal oxide, wherein the crystal region is an epitaxially grown layer from a crystal plane of the crystal substrate.
SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
The present disclosure relates to a semiconductor device including an n-type gallium oxide semiconductor layer that has a center region and a peripheral region having a lower donor density than the center region, an electrode layer that is laminated on the n-type gallium oxide semiconductor layer, and forms Schottky junction with the n-type gallium oxide semiconductor layer in the center region as viewed from a lamination direction, and a first p-type nickel oxide semiconductor layer that is laminated on the n-type gallium oxide semiconductor layer such that the first p-type nickel oxide semiconductor layer is partially positioned between the n-type gallium oxide semiconductor layer and the electrode layer, and has an outer peripheral end portion on a peripheral region side in the peripheral region as viewed from the lamination direction.
SEMICONDUCTOR MODULE AND METHOD FOR MANUFACTURING THE SAME
Disclosed is a semiconductor module including a substrate, a first semiconductor layer positioned on the substrate, an insulator positioned in a partial region on the first semiconductor layer, a second semiconductor layer positioned on the insulator, a first semiconductor device formed on the first semiconductor layer, and a second semiconductor device formed on the second semiconductor layer, wherein one of the first semiconductor layer and the second semiconductor layer includes gallium oxide (Ga.sub.2O.sub.3) and the other includes silicon (Si).
Semiconductor Module and Method for Manufacturing the Same
An embodiment semiconductor module includes a substrate, a heterogeneous thin film including a first semiconductor layer disposed on a first region of the substrate and a second semiconductor layer disposed on a second region of the substrate, a first semiconductor device disposed on the first semiconductor layer of the heterogeneous thin film, and a second semiconductor device disposed on the second semiconductor layer of the heterogeneous thin film, wherein one of the first semiconductor layer or the second semiconductor layer comprises gallium oxide (Ga.sub.2O.sub.3) and the other includes silicon (Si).