A method of producing a semiconductor laminate film includes forming a semiconductor layer containing silicon and germanium on a silicon substrate by a sputtering method. In the sputtering method, a film formation temperature of the semiconductor layer is less than 500° C., and a film formation pressure of the semiconductor layer ranges from 1 mTorr to 11 mTorr, or, a film formation temperature of the semiconductor layer is less than 600° C., and a film formation pressure of the semiconductor layer is equal to or more than 2 mTorr and less than 5 mTorr. The sputtering method uses a sputtering gas having a volume ratio of a hydrogen gas of less than 0.1%, and the semiconductor layer satisfies a relationship of t≤0.881×x.sup.−4.79, where t represents a thickness (nm) of the semiconductor layer, and x represents a ratio of the number of germanium atoms to a sum of the number of silicon atoms and the number of germanium atoms in the semiconductor layer.

An integrated circuit structure comprises a substrate having a memory region of and an adjacent logic region. A first N type well (Nwell) is formed in the substrate for the memory region and a second Nwell formed in the substrate for the logic region. A plurality of memory transistors in the memory region and a plurality of logic transistors are in the logic region, wherein ones the memory transistors include a floating gate over a channel, and a source and a drain on opposite sides of the channel. A diode portion is formed over one of the source and the drain of at least one of the memory transistors to conduct charge to the floating-gate of the at least one of the memory transistors for state retention during power gating.

An integrated circuit structure comprises a substrate having a memory region of and an adjacent logic region. A first N type well (Nwell) is formed in the substrate for the memory region and a second Nwell formed in the substrate for the logic region. A plurality of memory transistors in the memory region and a plurality of logic transistors are in the logic region, wherein ones the memory transistors include a floating gate over a channel, and a source and a drain on opposite sides of the channel. A diode portion is formed over one of the source and the drain of at least one of the memory transistors to conduct charge to the floating-gate of the at least one of the memory transistors for state retention during power gating.

A physically unclonable function (PUF) device 1 capable of exhibiting a unique quantum mechanical effect as a result of quantum mechanical confinement exhibited by the device 1. The device 1 comprises a group IV semiconductor heterostructure. The group IV semiconductor heterostructure may comprise Silicon/Germanium. The device 1 may comprise a group IV semiconductor resonant tunnelling diode (RTD). A Si-integrated circuit, method, use, and apparatus are also provided.

A metal-insulator-semiconductor-insulator-metal (MISIM) device includes a semiconductor layer, an insulating layer disposed over an upper surface of the semiconductor layer, a back electrode disposed over a lower surface of the semiconductor layer opposing the upper surface, and first and second electrodes disposed over the insulating layer and spaced-apart from each other.

A metal-insulator-semiconductor-insulator-metal (MISIM) device includes a semiconductor layer, an insulating layer disposed over an upper surface of the semiconductor layer, a back electrode disposed over a lower surface of the semiconductor layer opposing the upper surface, and first and second electrodes disposed over the insulating layer and spaced-apart from each other.

In one general embodiment, a structure includes a first diode, comprising: a first layer having a first type of dopant, and a second layer above the first layer, the second layer having a second type of dopant that is opposite to the first type of dopant. A second diode is formed directly on the first diode. The second diode comprises a first layer having a third type of dopant and a second layer above the first layer of the second diode, the second layer of the second diode having a fourth type of dopant that is opposite to the third type of dopant. In another general embodiment, a process includes a repeated sequence of growing a first layer having a first type of electrically active dopant and growing a second layer having a second type of electrically active dopant that is opposite to the first type of dopant.

A SRAM cell structure includes a plurality of transistors, a set of contacts, a word-line, a bit-line, a VDD contacting line and a VSS contacting line. The plurality of transistors include n transistors, wherein n is a positive integral less than 6. The set of contacts are coupled to the plurality of transistors. The word-line is electrically coupled to the plurality of transistors. The bit-line and a bit line bar are electrically coupled to the plurality of transistors. The VDD contacting line is electrically coupled to the plurality of transistors. The VSS contacting line is electrically coupled to the plurality of transistors. Wherein as a minimum feature size of the SRAM cell structure gradually decreases from 28 nm, an area size of the SRAM cell in terms of square of the minimum feature size (λ) is the same or substantially the same.

A SRAM cell structure includes a plurality of transistors, a set of contacts, a word-line, a bit-line, a VDD contacting line and a VSS contacting line. The plurality of transistors include n transistors, wherein n is a positive integral less than 6. The set of contacts are coupled to the plurality of transistors. The word-line is electrically coupled to the plurality of transistors. The bit-line and a bit line bar are electrically coupled to the plurality of transistors. The VDD contacting line is electrically coupled to the plurality of transistors. The VSS contacting line is electrically coupled to the plurality of transistors. Wherein as a minimum feature size of the SRAM cell structure gradually decreases from 28 nm, an area size of the SRAM cell in terms of square of the minimum feature size (λ) is the same or substantially the same.

Described herein are methods for using remote plasma chemical vapor deposition (RP-CVD) and sputtering deposition to grow layers for light emitting devices. A method includes growing a light emitting device structure on a growth substrate, and growing a tunnel junction on the light emitting device structure using at least one of RP-CVD and sputtering deposition. The tunnel junction includes a p++ layer in direct contact with a p-type region, where the p++ layer is grown by using at least one of RP-CVD and sputtering deposition. Another method for growing a device includes growing a p-type region over a growth substrate using at least one of RP-CVD and sputtering deposition, and growing further layers over the p-type region. Another method for growing a device includes growing a light emitting region and an n-type region using at least one of RP-CVD and sputtering deposition over a p-type region.