Devices, methods and techniques are disclosed for providing a multi-layer diode without voids between layers. In one example aspect, a multi-stack diode includes at least two Drift Step Recovery Diodes (DSRDs). Each DSRD comprises a first layer having a first type of dopant, a second layer forming a region with at least ten times lower concentration of dopants compared to the adjacent layers, and a third layer having a second type of dopant that is opposite to the first type of dopant. The first layer of a second DSRD is positioned on top of the third layer of first DSRD. The first layer of the second DSRD and the third layer of the first DSRD are degenerate to form a tunneling diode at an interface of the first DSRD and second DSRD, the tunneling diode demonstrating a linear current-voltage characteristic.

Devices, methods and techniques are disclosed for providing a multi-layer diode without voids between layers. In one example aspect, a multi-stack diode includes at least two Drift Step Recovery Diodes (DSRDs). Each DSRD comprises a first layer having a first type of dopant, a second layer forming a region with at least ten times lower concentration of dopants compared to the adjacent layers, and a third layer having a second type of dopant that is opposite to the first type of dopant. The first layer of a second DSRD is positioned on top of the third layer of first DSRD. The first layer of the second DSRD and the third layer of the first DSRD are degenerate to form a tunneling diode at an interface of the first DSRD and second DSRD, the tunneling diode demonstrating a linear current-voltage characteristic.

A device includes a substrate, a first electrode and a second electrode. The first electrode is disposed on the substrate, and configured to receive an input signal. The second electrode is disposed on the substrate, and configured to output an output signal based on the input signal. When the input signal is configured to oscillate within a first range between a first voltage value and a second voltage value with a first frequency, the output signal is an inverted version of the input signal, and has the first frequency. When the input signal is configured to oscillate within a second range including the first voltage value without the second voltage value with the first frequency, the output signal has a second frequency which is approximately twice of the first frequency.

A resonant tunneling diode includes a substrate, and a mesa structure including a compound semiconductor layer including a heterojunction comprising a multi-barrier structure disposed on the substrate, and an electrode disposed on the upper surface of the compound semiconductor layer. An outer edge portion of the compound semiconductor layer is a first region including crystal defects, and the first region and the electrode are set apart from each other.

One or more devices and/or methods provided herein relate to a method for fabricating a semiconductor device having a co-integrated RTD and HEMT. A semiconductor device can comprise an RTD and an HEMT that are co-integrated along a substrate. A fabrication method can comprise providing a heterostructure comprising a plurality of transistor layers of an HEMT, forming on the vertical stack a template structure comprising an opening, a cavity and a seed structure, the seed structure comprising a seed material and a seed surface, and growing a plurality of diode layers of an RTD within the cavity of the template structure from the seed surface, wherein the RTD and HEMT are co-integrated along a substrate.

One or more systems, devices and/or methods provided herein relate to a device that can facilitate generation of a pulse to affect a qubit and to a method that can facilitate fabrication of a semiconductor device. The semiconductor device can comprise an RTD and an FET co-integrated in a common layer extending along a substrate. A method for fabricating the semiconductor device can comprise applying, at a substrate layer, a template structure comprising an opening, a cavity and a seed structure comprising a seed material and a seed surface, and sequentially growing along the substrate a plurality of diode layers of an RTD and a plurality of transistor layers of an FET within the cavity of the template structure from the seed surface, wherein the RTD and FET are co-integrated along the substrate.

The present disclosure provides a resonant tunneling diode and a manufacturing method thereof. The resonant tunneling diode includes: a first barrier layer; a second barrier layer; and a potential well layer between the first barrier layer and the second barrier layer, a material of the first barrier layer being Al.sub.xIn.sub.yN.sub.1-x-y, 1>x>0, 1>y>0, and/or a material of the second barrier layer being Al.sub.mIn.sub.nN.sub.1-m-n, 1>m>0, 1>n>0, and a material of the well layer including a gallium element.

The present disclosure provides a resonant tunneling diode and a manufacturing method thereof. The resonant tunneling diode includes: a first barrier layer; a second barrier layer; and a potential well layer between the first barrier layer and the second barrier layer, a material of the first barrier layer being Al.sub.xIn.sub.yN.sub.1-x-y, 1>x>0, 1>y>0, and/or a material of the second barrier layer being Al.sub.mIn.sub.nN.sub.1-m-n, 1>m>0, 1>n>0, and a material of the well layer including a gallium element.

A cross-coupled tunnel diode (XTD) device with large peak-to-valley current ratio (PVCR) is disclosed. A memory cell circuit comprising XTD devices is also disclosed. The XTD device includes an N-type semiconductor coupled to a P-type semiconductor. A first gate is disposed on the N-type semiconductor and a second gate is disposed on the P-type semiconductor. The first gate is coupled to the output terminal, which is further coupled to the P-type semiconductor. The second gate is coupled to the input terminal, which is coupled to the N-type semiconductor. As reverse bias voltage increases, band-to-band tunneling from valence band to conduction band initially generates increasing current, but the rising bias voltage closes the band to band tunneling window, creating a gated negative differential resistance behavior. The current drops off as the bias voltage further increases. In some examples, a ratio of peak-to-valley current ratio may exceed 10.sup.3 or 10.sup.5.

A cross-coupled tunnel diode (XTD) device with large peak-to-valley current ratio (PVCR) is disclosed. A memory cell circuit comprising XTD devices is also disclosed. The XTD device includes an N-type semiconductor coupled to a P-type semiconductor. A first gate is disposed on the N-type semiconductor and a second gate is disposed on the P-type semiconductor. The first gate is coupled to the output terminal, which is further coupled to the P-type semiconductor. The second gate is coupled to the input terminal, which is coupled to the N-type semiconductor. As reverse bias voltage increases, band-to-band tunneling from valence band to conduction band initially generates increasing current, but the rising bias voltage closes the band to band tunneling window, creating a gated negative differential resistance behavior. The current drops off as the bias voltage further increases. In some examples, a ratio of peak-to-valley current ratio may exceed 10.sup.3 or 10.sup.5.