The present disclosure provides a semiconductor device and a method of manufacturing a semiconductor device. The semiconductor device comprises a substrate, a first gate electrode, a second gate electrode, a first doped region, a second doped region, a third doped region, and a first interconnection structure. The substrate comprises a well region of a first conductive type. The first and second gate electrodes are disposed on the substrate. The first, second, and third doped regions are embedded within the well region and are of the first conductive type. The first interconnection structure electrically connects the first gate electrode and the second gate electrode. The first doped region and the second doped region are disposed on opposite sides of the first gate electrode.

A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate, wherein the isolation feature is adjacent to the channel. The low noise device further includes a spacer surrounding a portion of the gate stack, wherein an edge of the gate stack is spaced from an edge of the isolation feature adjacent to the spacer by a distance ranging from a minimum spacing distance to about 0.3 microns (μm).

A low noise device includes an isolation feature in a substrate. The low noise device further includes a gate stack over a channel in the substrate, wherein the isolation feature is adjacent to the channel. The low noise device further includes a spacer surrounding a portion of the gate stack, wherein an edge of the gate stack is spaced from an edge of the isolation feature adjacent to the spacer by a distance ranging from a minimum spacing distance to about 0.3 microns (μm).

An electronic device is provided. The electronic device includes a pixel array, a gate driver and a bias signal driver. The pixel array includes a pixel unit. The gate driver generates a plurality of gate control signals. The bias signal driver is electrically connected to the pixel unit and the gate driver, and configured to generate a bias signal to activate the pixel unit according to a part of the plurality of gate control signals. The bias signal driver includes a first logic circuit and a second logic circuit.

An electronic device is provided. The electronic device includes a pixel array, a gate driver and a bias signal driver. The pixel array includes a pixel unit. The gate driver generates a plurality of gate control signals. The bias signal driver is electrically connected to the pixel unit and the gate driver, and configured to generate a bias signal to activate the pixel unit according to a part of the plurality of gate control signals. The bias signal driver includes a first logic circuit and a second logic circuit.

The disclosure provides an electromagnetic wave adjustment apparatus includes a control circuit, a transistor circuit die and an electronic assembly. The transistor circuit die receives a control signal from the control circuit and drives the electronic assembly.

The disclosure provides an electromagnetic wave adjustment apparatus includes a control circuit, a transistor circuit die and an electronic assembly. The transistor circuit die receives a control signal from the control circuit and drives the electronic assembly.

The disclosure provides an electronic apparatus. The electronic apparatus includes a substrate, a first metal layer, an insulating layer, a first conductor, an electronic assembly and a transistor circuit die. The first metal layer is disposed on the substrate. The insulating layer is disposed on the substrate. The first conductor is formed in a first via of the insulating layer. The electronic assembly is disposed on the substrate and electrically connected to the first metal layer through the first conductor. The transistor circuit die is electrically connected to the first metal layer.

The disclosure provides an electronic apparatus. The electronic apparatus includes a substrate, a first metal layer, an insulating layer, a first conductor, an electronic assembly and a transistor circuit die. The first metal layer is disposed on the substrate. The insulating layer is disposed on the substrate. The first conductor is formed in a first via of the insulating layer. The electronic assembly is disposed on the substrate and electrically connected to the first metal layer through the first conductor. The transistor circuit die is electrically connected to the first metal layer.

Gate-all-around integrated circuit structures including varactors are described. For example, an integrated circuit structure includes a varactor structure on a semiconductor substrate. The varactor structure includes a plurality of discrete vertical arrangements of horizontal nanowires. A plurality of gate stacks is over and surrounding corresponding ones of the plurality of discrete vertical arrangements of horizontal nanowires. The integrated circuit structure also includes a tap structure adjacent to the varactor structure on the semiconductor substrate. The tap structure includes a plurality of merged vertical arrangements of horizontal nanowires. A plurality of semiconductor structures is over and surrounding corresponding ones of the plurality of merged vertical arrangements of horizontal nanowires.