Provided are a semiconductor structure and a method for forming same. The method includes the following operations. Active areas and first isolation structures disposed at intervals are provided. Second isolation structures located between adjacent active areas are provided, and top surfaces of the second isolation structures are higher than or flush with top surfaces of the active areas. A mask layer are formed, pattern openings of which expose part of the top surfaces of the active areas, and the second isolation structures are located at two opposite sides of part of the active areas. The part of the active areas exposed by the pattern openings and part of the first isolation structures are etched to form intermediate grooves at least exposing part of surfaces of the active areas. Bit line structures are formed, which are electrically connected to top surfaces exposed by the intermediate grooves.

Disclosed herein is an apparatus that includes a plurality of cell capacitors arranged in a memory cell array region of a semiconductor substrate, each of the plurality of cell capacitors having a first electrode, a second electrode and an insulating film therebetween to electrically disconnect the first and second electrodes, a first conductive member including the plurality of cell capacitors therein, the first conductive member being electrically connected in common to the first electrodes of the plurality of cell capacitors, and a second conductive member formed on an upper surface of the first conductive member, a material of the second conductive member being different from that of the first conductive member. A side surface of the first conductive member is free from the second conductive member.

The disclosure provides a semiconductor memory device and a method of forming a semiconductor device. The semiconductor memory device includes a substrate and a first pattern. The first pattern is disposed on the substrate and extends along a first direction. The first pattern includes an extension portion and two end portions. The two end portions include a first end pattern and a second end pattern, respectively. The extension portion has a first width. The first end pattern includes an outer widened portion and an inner widened portion. The maximum width of the outer widened portion and the maximum width of the inner widened portion are different from each other, and both are greater than the first width of the extension portion of the first pattern.

Embodiments disclose a buried bit line structure, a method for fabricating the buried bit line structure, and a memory. The buried bit line structure includes: a substrate having a bit line trench; a bit line metal filled in the bit line trench; and a bit line contact filled in the bit line trench and positioned on the bit line metal, where an arc-shaped contact surface is provided between the bit line contact and the bit line metal. By setting a contact surface between the bit line contact and the bit line metal to be the arc-shaped contact surface, a contact area between the bit line contact and the bit line metal is increased, electrical conductivity of the bit line structure is enhanced.

A semiconductor device includes a bit line structure and a storage contact spaced apart from each other over a substrate; a bit line spacer formed on a sidewall of the bit line structure; a landing pad formed over the storage contact; a boron-containing capping layer disposed between the bit line structure and the landing pad; a boron-containing etch stop layer over the boron-containing capping layer; and a capacitor including a storage node coupled to the landing pad by passing through the boron-containing etch stop layer.

A method of forming a semiconductor device includes: depositing a first conductive plate and a second conductive plate adjacent to the first conductive plate; depositing a first insulating plate on the first conductive plate and the second conductive plate; depositing a third conductive plate on the first insulating plate; depositing a second insulating plate on the third conductive plate; forming a fourth conductive plate on the second insulating plate; forming a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate; and forming a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate.

A method of forming a semiconductor device includes: depositing a first conductive plate and a second conductive plate adjacent to the first conductive plate; depositing a first insulating plate on the first conductive plate and the second conductive plate; depositing a third conductive plate on the first insulating plate; depositing a second insulating plate on the third conductive plate; forming a fourth conductive plate on the second insulating plate; forming a first conductive via penetrating the fourth conductive plate, the second insulating plate, the first insulating plate, and the first conductive plate; and forming a second conductive via penetrating the second insulating plate, the third conductive plate, the first insulating plate, and the second conductive plate.

A varactor transistor includes a semiconductor fin having a first conductivity type, a plurality of gate structures separated from each other and surrounding a portion of the semiconductor fin. The plurality of gates structures include a dummy gate structure on an edge of the semiconductor fin, and a first gate structure spaced apart from the dummy gate structure. The dummy gate structure and the gate structure each include a gate insulator layer on a surface portion of the semiconductor fin, a gate on the gate insulator layer, and a spacer on the gate. The varactor transistor also includes a raised source/drain region on the semiconductor fin and between the dummy gate structure and the first gate structure, the raised source/drain region and the gate of the dummy gate structure being electrically connected to a same potential.

Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.

Dual gate FD-SOI transistors are used as MOSFET capacitors to replace passive well capacitors in analog microcircuits. Use of the dual gate FD-SOI devices helps to reduce unstable oscillations and improve circuit performance. A thick buried oxide layer within the substrate of an FD-SOI transistor forms a capacitive dielectric that can sustain high operating voltages in the range of 1.2 V-3.3 V, above the transistor threshold voltage. A secondary gate in the FD-SOI transistor is used to create a channel from the back side so that even when the bias voltage on the first gate is small, the effective capacitance remains higher. The capacitance of the buried oxide layer is further utilized as a decoupling capacitor between supply and ground. In one example, a dual gate PMOS FD-SOI transistor is coupled to an operational amplifier and a high voltage output driver to produce a precision-controlled voltage reference generator. In another example, two dual gate PMOS and one dual gate NMOS FD-SOI transistor are coupled to a charge pump, a phase frequency detector, and a current-controlled oscillator to produce a high-performance phase locked loop circuit in which the decoupling capacitor footprint is smaller, in comparison to the conventional usage of passive well capacitance.