A semiconductor structure, a method for manufacturing a semiconductor structure, and a memory are provided. The semiconductor structure includes: a plurality of first semiconductor pillars, a plurality of second semiconductor pillars, a first support layer, and a storage structure. The plurality of first semiconductor pillars are arranged in an array in a first direction and in a second direction. Each of the first direction and the second direction is perpendicular to an extending direction of each first semiconductor pillar, and the first direction intersects with the second direction. The first support layer covers sidewalls of top portions of the plurality of first semiconductor pillars. Each second semiconductor pillar is arranged on a respective one of the plurality of first semiconductor pillars. The storage structure is arranged around at least sidewalls of the plurality of first semiconductor pillars and sidewalls of the plurality of second semiconductor pillars.

A method for forming a semiconductor structure comprises: providing a substrate, which includes a first area and a second area arranged in sequence in a second direction, the first area including active layers arranged at intervals in a third direction; forming an initial gate structure located on a surface of each active layer in the first area; etching the initial gate structures to form comb-shaped gate structures stacked in a third direction, each comb-shaped gate structure including first gate structures arranged at intervals in the first direction; and forming bit line structures extending in the third direction and capacitor structures extending in the second direction in the second area, the bit line structures and the capacitor structures are connecting to the first gate structures.

A method for forming a semiconductor structure includes the following: a substrate is provided, the substrate including a first area and a second area arranged in sequence in a second direction and T-shaped active pillars located in the first area and the second area and arranged in an array in a first direction and a third direction, the first, second and third directions being perpendicular to one another, and the first and second directions being parallel to a surface of the substrate; T-shaped gate structures located on surfaces of the T-shaped active pillars and bit line structures extending in the third direction are formed in the first area, a plurality of T-shaped gate structures located in the first direction being interconnected; and capacitor structures extending in the second direction is formed in the second area, the bit line structures and the capacitor structures being connected to the T-shaped gate structures.

The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The method of manufacturing the semiconductor structure includes: providing a substrate; forming, on the substrate, a first initial conductive layer, a sacrificial layer and a first mask layer with a pattern that are stacked sequentially, a thickness of the sacrificial layer being 10 nm-20 nm; and etching, with the first mask layer as a mask, the first initial conductive layer and the substrate to form a bit line (BL) contact region.

A capacitor includes: a bottom electrode; a top electrode over the bottom electrode; a dielectric film between the bottom electrode and the top electrode; and a doped Al.sub.2O.sub.3 film between the top electrode and the dielectric film, wherein the doped Al.sub.2O.sub.3 film includes a first dopant, and an oxide including the same element as the first dopant has a higher dielectric constant than a dielectric constant of Al.sub.2O.sub.3.

There is provided a high dielectric film including amorphous hydrocarbon of which a dielectric constant is 10 or more. A leakage current of the high dielectric film is 1 A/cm.sup.2 or less, and an insulation level is 1 MV/cm or more. Rms surface roughness of the high dielectric film is 20 nm or less.

There is provided a high dielectric film including amorphous hydrocarbon of which a dielectric constant is 10 or more. A leakage current of the high dielectric film is 1 A/cm.sup.2 or less, and an insulation level is 1 MV/cm or more. Rms surface roughness of the high dielectric film is 20 nm or less.

A method for manufacturing a semiconductor structure includes the following operations. A substrate is provided, and is etched to form first isolation trenches in a cell region and a second isolation trench in a peripheral region. A first isolation dielectric layer is filled in each of the first isolation trenches and an isolation structure is formed in the second isolation trench. A patterned mask layer is formed on surfaces of the cell region and the peripheral region. The substrate and the first isolation dielectric layer are etched based on the patterned mask layer to form the third isolation trenches extending along a second direction. The third and first isolation trenches isolate multiple active pillars. The active pillar includes a first connecting end, a second connecting end and a channel region.

Provide is a method for manufacturing a semiconductor structure, a semiconductor structure, and a semiconductor memory. The method includes the following operations. A substrate is provided. Multiple silicon pillars are formed in the substrate, and extend along a first direction. In the first direction, each of the silicon pillars includes a first portion and a second portion. An insulating layer is formed in the second portion of the silicon pillar. A conductive layer is formed in the first portion of the silicon pillar. A capacitor layer is formed on surfaces of the insulating layer and the conductive layer of the silicon pillar.

The present disclosure provides a method of manufacturing a semiconductor structure. The method includes providing a substrate; forming a trench with a predetermined aspect ratio in the substrate to form two fins, wherein the forming of the trench induces the substrate to warp toward a first direction; forming a metal-insulator-metal (MIM) stack on sidewalls of the two fins in the trench, and leaving a space surrounded by the MIM stack in the trench; determining whether the substrate warps toward a second direction reverse to the first direction after the forming of the MIM stack; and in response to the substrate warping toward the second direction, depositing an insulating layer to cover an upper surface of the MIM stack and seal the trench to thereby leave a void in the space.