Embodiments of a hybrid imaging sensor that optimizes a pixel array area on a substrate using a stacking scheme for placement of related circuitry with minimal vertical interconnects between stacked substrates and associated features are disclosed. Embodiments of maximized pixel array size/die size (area optimization) are disclosed, and an optimized imaging sensor providing improved image quality, improved functionality, and improved form factors for specific applications common to the industry of digital imaging are also disclosed.

An electromagnetic wave detector includes: a substrate; an insulating layer provided on the substrate; a graphene layer provided on the insulating layer; a pair of electrodes provided on the insulating layer, with the graphene layer being interposed therebetween; and buffer layers interposed between the graphene layer and the electrodes to separate the graphene layer and the electrodes from each other. The electromagnetic wave detector array includes arrayed electromagnetic wave detectors that are the same as or different from each other.

An electromagnetic wave detector includes: a substrate; an insulating layer provided on the substrate; a graphene layer provided on the insulating layer; a pair of electrodes provided on the insulating layer, with the graphene layer being interposed therebetween; and buffer layers interposed between the graphene layer and the electrodes to separate the graphene layer and the electrodes from each other. The electromagnetic wave detector array includes arrayed electromagnetic wave detectors that are the same as or different from each other.

The present application relates to semiconductor photodetectors, in particular to a silicon carbide-based UV-visible-NIR full-spectrum-responsive photodetector and a method for fabricating the same. The photodetector includes a silicon carbide substrate, and metal counter electrodes and a surface plasmon polariton nanostructure arranged thereon. The silicon carbide substrate and the metal counter electrodes constitute a metal-semiconductor-metal photodetector with coplanar electrodes. When the ultraviolet light is input, free carriers directly generated in silicon carbide are collected by an external circuit to generate electrical signals. When the visible light is input, hot carriers generated in the surface plasmon polariton nanostructure tunnel into the silicon carbide semiconductor to become free carriers to generate electrical signals.

The present invention provides a normal-incident photodiode structure with a dark current self-compensation function, including a photosensitive photodiode and a compensating photodiode, where a photosensitive surface of the compensating photodiode is provided with a light-blocking layer, and dark currents of the photosensitive photodiode and the compensating photodiode are equal. According to the present invention, the dark current self-compensation function may be implemented at a chip level without an external circuit and an operational amplifier; the normal-incident photodiode structure according to the present invention has the photosensitive photodiode and the compensating photodiode, and the compensating photodiode may counteract the dark current of the photosensitive photodiode during operation, thus reducing noise caused by the dark current of the photosensitive photodiode; and bias voltages of the photosensitive photodiode and the compensating photodiode according to the present invention are controlled separately, and thus may be applied to more usage scenarios.

The present invention provides a normal-incident photodiode structure with a dark current self-compensation function, including a photosensitive photodiode and a compensating photodiode, where a photosensitive surface of the compensating photodiode is provided with a light-blocking layer, and dark currents of the photosensitive photodiode and the compensating photodiode are equal. According to the present invention, the dark current self-compensation function may be implemented at a chip level without an external circuit and an operational amplifier; the normal-incident photodiode structure according to the present invention has the photosensitive photodiode and the compensating photodiode, and the compensating photodiode may counteract the dark current of the photosensitive photodiode during operation, thus reducing noise caused by the dark current of the photosensitive photodiode; and bias voltages of the photosensitive photodiode and the compensating photodiode according to the present invention are controlled separately, and thus may be applied to more usage scenarios.

Structures including a photodetector and methods of fabricating such structures. The photodetector is positioned over the top surface of the substrate. The photodetector includes a portion of a semiconductor layer comprised of a semiconductor alloy, a p-type doped region in the portion of the semiconductor layer, and an n-type doped region in the portion of the semiconductor layer. The p-type doped region and the n-type doped region converge along a p-n junction. The portion of the semiconductor layer has a first side and a second side opposite from the first side. The semiconductor alloy has a composition that is laterally graded from the first side to the second side of the portion of the semiconductor layer.

Structures including a photodetector and methods of fabricating such structures. The photodetector is positioned over the top surface of the substrate. The photodetector includes a portion of a semiconductor layer comprised of a semiconductor alloy, a p-type doped region in the portion of the semiconductor layer, and an n-type doped region in the portion of the semiconductor layer. The p-type doped region and the n-type doped region converge along a p-n junction. The portion of the semiconductor layer has a first side and a second side opposite from the first side. The semiconductor alloy has a composition that is laterally graded from the first side to the second side of the portion of the semiconductor layer.

The present disclosure relates a method of forming an integrated chip structure. The method includes etching a base substrate to form a recess defined by one or more interior surfaces of the base substrate. A doped epitaxial layer is formed along the one or more interior surfaces of the base substrate, and an epitaxial material is formed on horizontally and vertically extending surfaces of the doped epitaxial layer. A first doped photodiode region is formed within the epitaxial material and a second doped photodiode region is formed within the epitaxial material. The first doped photodiode region has a first doping type and the second doped photodiode region has a second doping type.

The present disclosure relates a method of forming an integrated chip structure. The method includes etching a base substrate to form a recess defined by one or more interior surfaces of the base substrate. A doped epitaxial layer is formed along the one or more interior surfaces of the base substrate, and an epitaxial material is formed on horizontally and vertically extending surfaces of the doped epitaxial layer. A first doped photodiode region is formed within the epitaxial material and a second doped photodiode region is formed within the epitaxial material. The first doped photodiode region has a first doping type and the second doped photodiode region has a second doping type.