Patent classifications
H01L31/03682
Optoelectronic semiconductor component
An optoelectronic semiconductor component is disclosed. In an embodiment an optoelectronic semiconductor component includes a front side, a first diode and a second diode arranged downstream of one another in a direction away from the front side and electrically connected in series such that the first diode is located closer to the front side than the second diode and an electrical tunnel contact between the first and the second diodes, wherein the second diode comprises a diode layer of Si.sub.nGe.sub.1-n, where 0≤n≤1, wherein the first diode comprises a first partial layer of SiGeC, a second partial layer of SiGe and a third partial layer of SiGeC, and wherein the partial layers follow one another directly in the direction away from the front side according to their numbering such that the first and third partial layers are of (Si.sub.yGe.sub.1-y).sub.1-xC.sub.x, whereas 0.05≤x≤0.5 or 0.25≤x≤0.75, and whereas 0≤y≤1, and the second partial layer is of SizGe1-z, whereas 0≤z≤1.
BLISTER-FREE POLYCRYSTALLINE SILICON FOR SOLAR CELLS
Described herein are methods of fabricating solar cells. In an example, a method of fabricating a solar cell includes forming an amorphous dielectric layer on the back surface of a substrate opposite a light-receiving surface of the substrate. The method also includes forming a microcrystalline silicon layer on the amorphous dielectric layer by plasma enhanced chemical vapor deposition (PECVD). The method also includes forming an amorphous silicon layer on the microcrystalline silicon layer by PECVD. The method also includes annealing the microcrystalline silicon layer and the amorphous silicon layer to form a homogeneous polycrystalline silicon layer from the microcrystalline silicon layer and the amorphous silicon layer. The method also includes forming an emitter region from the homogeneous polycrystalline silicon layer.
Trench process and structure for backside contact solar cells with polysilicon doped regions
A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.
Detection device
A detection device comprising: an insulating substrate; a plurality of gate lines that are provided on the insulating substrate, and extend in a first direction; a plurality of signal lines that are provided on the insulating substrate, and extend in a second direction intersecting the first direction; a switching element coupled to each of the gate lines and each of the signal lines; a first photoelectric conversion element that comprises a first semiconductor layer containing amorphous silicon, and is coupled to the switching element; and a second photoelectric conversion element that comprises a second semiconductor layer containing polysilicon, and is coupled to the switching element.
Photovoltage Field-Effect Transistor
In an embodiment, a photodetector is provided that provides a sensitizing medium adapted to receive electromagnetic radiation creating a junction with a transport channel, wherein the transport channel is adapted to exhibit a change in conductivity in response to reception of electromagnetic radiation by the sensitizing medium.
INTEGRATE STRESSOR WITH GE PHOTODIODE USING A SUBSTRATE REMOVAL PROCESS
The embodiments of the present disclosure describe a stressed Ge PD and fabrications techniques for making the same. In one embodiment, a stressor material is deposited underneath an already formed Ge PD. To do so, wafer bonding can be used to bond the wafer containing the Ge PD to a second, handler wafer. Doing so provides support to remove the substrate of the wafer so that a stressor material (e.g., silicon nitride, diamond-like carbon, or silicon-germanium) can be disposed underneath the Ge PD. The stress material induces a stress or strain in the crystal lattice of the Ge which changes its bandgap and improves its responsivity.
DOPED REGION STRUCTURE AND SOLAR CELL COMPRISING THE SAME, CELL ASSEMBLY, AND PHOTOVOLTAIC SYSTEM
The disclosure relates to the technical field of solar cells, and provides a solar cell and a doped region structure thereof, a cell assembly, and a photovoltaic system. The doped region structure includes a first doped layer, a passivation layer, and a second doped layer that are disposed on a silicon substrate in sequence. The passivation layer is a porous structure having the first doped layer and/or the second doped layer inlaid in a hole region. The first doped layer and the second doped layer have a same doping polarity. By means of the doped region structure of the solar cell provided in the disclosure, the difficulty in production and the limitation on conversion efficiency as a result of precise requirements for the accuracy of a thickness of a conventional tunneling layer are resolved.
SOLAR CELL
A method for manufacturing a solar cell, includes providing a silicon substrate, forming an oxide layer on a first surface of the silicon substrate, forming a doped polycrystalline silicon layer on the oxide layer, forming a passivation layer on the doped polycrystalline silicon layer, printing a metal paste on the passivation layer, and forming a metal contact connected to the doped polycrystalline silicon layer by firing the metal paste to penetrate the passivation layer.
SOLAR CELL
Discussed is a solar cell including a silicon substrate, an emitter area formed on a front surface of the silicon substrate, a tunneling oxide layer formed on a back surface of the silicon substrate, a back surface field area formed on the tunneling oxide layer and formed of a polycrystalline silicon layer, a front passivation film on the emitter area, a front electrode connected to the emitter area by penetrating through the front passivation film, a back passivation film formed on the back surface field area and having an opening and a back electrode connected to the back surface field area via the opening.
Conductive contacts for polycrystalline silicon features of solar cells
Methods of fabricating conductive contacts for polycrystalline silicon features of solar cells, and the resulting solar cells, are described. In an example, a method of fabricating a solar cell includes providing a substrate having a polycrystalline silicon feature. The method also includes forming a conductive paste directly on the polycrystalline silicon feature. The method also includes firing the conductive paste at a temperature above approximately 700 degrees Celsius to form a conductive contact for the polycrystalline silicon feature. The method also includes, subsequent to firing the conductive paste, forming an anti-reflective coating (ARC) layer on the polycrystalline silicon feature and the conductive contact. The method also includes forming a conductive structure in an opening through the ARC layer and electrically contacting the conductive contact.