Patent classifications
H01L31/03682
MULTILEVEL SEMICONDUCTOR DEVICE AND STRUCTURE
A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including an optical waveguide, where the second level is disposed above the first level, where the first level includes crystalline silicon; and an oxide layer disposed between the first level and the second level, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.
Crystalline silicon solar cell, production method therefor, and solar cell module
A crystalline silicon-based solar cell includes a crystalline silicon substrate having a first principal surface, a second principal surface, and a lateral surface. On the first principal surface is arranged, in the following order, a first intrinsic silicon-based thin-film, a first conductive silicon-based thin-film, a light-receiving-side transparent electrode layer and a light-receiving-side metal electrode. On the second principal surface is arranged, in the following order, a second intrinsic silicon-based thin-film, a second conductive silicon-based thin-film, a back-side transparent electrode layer and a back-side metal electrode. The second conductive silicon-based thin-film has a conductivity-type different from that of the first conductive silicon-based thin-film. Both the first principal surface and the second principal surface are textured. Both the light-receiving-side metal electrode and the back-side metal electrode have a pattern shape. The back-side transparent electrode layer is not provided on a peripheral edge of the second principal surface.
PHOTODETECTION FILM, PHOTODETECTION DEVICE AND PHOTODETECTION DISPLAY APPARATUS INCLUDING PHOTODETECTION FILM, AND METHODS OF MAKING PHOTODETECTION FILM AND PHOTODETECTION DEVICE
A photodetection film includes at least one lower photodiode and upper photodiode layered members. The at least one lower photodiode layered member includes lower first-type, intrinsic and second-type semiconductor layers. The at least one upper photodiode layered member is disposed on the at least one lower photodiode layered member and includes upper first-type, intrinsic and second-type semiconductor layers. The upper intrinsic semiconductor layer has an amorphous silicon structure. The lower intrinsic semiconductor layer has a structure selected from one of a microcrystalline silicon structure, a microcrystalline silicon-germanium structure, and a non-crystalline silicon-germanium structure.
HYBRID POLYSILICON HETEROJUNCTION BACK CONTACT CELL
A method for manufacturing high efficiency solar cells is disclosed. The method comprises providing a thin dielectric layer and a doped polysilicon layer on the back side of a silicon substrate. Subsequently, a high quality oxide layer and a wide band gap doped semiconductor layer can both be formed on the back and front sides of the silicon substrate. A metallization process to plate metal fingers onto the doped polysilicon layer through contact openings can then be performed. The plated metal fingers can form a first metal gridline. A second metal gridline can be formed by directly plating metal to an emitter region on the back side of the silicon substrate, eliminating the need for contact openings for the second metal gridline. Among the advantages, the method for manufacture provides decreased thermal processes, decreased etching steps, increased efficiency and a simplified procedure for the manufacture of high efficiency solar cells.
Solar cells with tunnel dielectrics
A solar cell can have a first dielectric formed over a first doped region of a silicon substrate. The solar cell can have a second dielectric formed over a second doped region of the silicon substrate, where the first dielectric is a different type of dielectric than the second dielectric. A doped semiconductor can be formed over the first and second dielectric. A positive-type metal and a negative-type metal can be formed over the doped semiconductor.
IN-CELL BYPASS DIODE
A solar cell can include a built-in bypass diode. In one embodiment, the solar cell can include an active region disposed in or above a first portion of a substrate and a bypass diode disposed in or above a second portion of the substrate. The first and second portions of the substrate can be physically separated with a groove. A metallization structure can couple the active region to the bypass diode.
In-cell bypass diode
A solar cell can include a built-in bypass diode. In one embodiment, the solar cell can include an active region disposed in or above a first portion of a substrate and a bypass diode disposed in or above a second portion of the substrate. The first and second portions of the substrate can be physically separated with a groove. A metallization structure can couple the active region to the bypass diode.
Polycrystalline silicon column and polycrystalline silicon wafer
A polycrystalline silicon wafer is provided. The polycrystalline silicon wafer, includes a plurality of silicon grains, wherein the carbon content of the polycrystalline silicon wafer is greater than 4 ppma, and the resistivity of the polycrystalline silicon wafer is greater than or equal to 1.55 -cm.
Method and system for optoelectronic receivers utilizing waveguide heterojunction phototransistors integrated in a CMOS SOI wafer
A method and system for optoelectronic receivers utilizing waveguide heterojunction phototransistors (HPTs) integrated in a wafer are disclosed and may include receiving optical signals via optical fibers operably coupled to a top surface of the chip. Electrical signals may be generated utilizing HPTs that detect the optical signals. The electrical signals may be amplified via voltage amplifiers, or transimpedance amplifiers, the outputs of which may be utilized to bias the HPTs by a feedback network. The optical signals may be coupled into opposite ends of the HPTs. A collector of the HPTs may comprise a silicon layer and a germanium layer, a base may comprise a silicon germanium alloy with germanium composition ranging from 70% to 100%, and an emitter including crystalline or poly Si or SiGe.
FLUID SENSOR AND METHOD FOR MANUFACTURING A FLUID SENSOR
A fluid sensor includes a substrate having a top main surface region, wherein the top main surface region of the substrate forms a common system plane of the fluid sensor, a thermal radiation emitter on the top main surface region of the substrate, an optical filter structure on the top main surface region of the substrate, a waveguide on the main top surface region of the substrate, and a thermal radiation detector on the top main surface region of the substrate, wherein the thermal radiation detector provides a detector output signal based on a radiation strength of the filtered thermal radiation received from the waveguide.