Patent classifications
H01L31/0682
BLISTER-FREE POLYCRYSTALLINE SILICON FOR SOLAR CELLS
Described herein are methods of fabricating solar cells. In an example, a method of fabricating a solar cell includes forming an amorphous dielectric layer on the back surface of a substrate opposite a light-receiving surface of the substrate. The method also includes forming a microcrystalline silicon layer on the amorphous dielectric layer by plasma enhanced chemical vapor deposition (PECVD). The method also includes forming an amorphous silicon layer on the microcrystalline silicon layer by PECVD. The method also includes annealing the microcrystalline silicon layer and the amorphous silicon layer to form a homogeneous polycrystalline silicon layer from the microcrystalline silicon layer and the amorphous silicon layer. The method also includes forming an emitter region from the homogeneous polycrystalline silicon layer.
SOLAR CELL EMITTER REGION FABRICATION USING SUBSTRATE-LEVEL ION IMPLANTATION
Methods of fabricating solar cell emitter regions using substrate-level ion implantation, and resulting solar cells, are described. In an example, a method of fabricating a solar cell involves forming a lightly doped region in a semiconductor substrate by ion implantation, the lightly doped region of a first conductivity type of a first concentration. The method also involves forming a first plurality of dopant regions of the first conductivity type of a second, higher, concentration by ion implantation, the first plurality of dopant regions overlapping with a first portion of the lightly doped region. The method also involves forming a second plurality of dopant regions by ion implantation, the second plurality of dopant regions having a second conductivity type of a concentration higher than the first concentration, and the second plurality of dopant regions overlapping with a second portion of the lightly doped region and alternating with but not overlapping the first plurality of dopant regions.
ROLL-TO-ROLL METALLIZATION OF SOLAR CELLS
Disclosed herein are approaches to fabricating solar cells, solar cell strings and solar modules using roll-to-roll foil-based metallization approaches. Methods disclosed herein can comprise the steps of providing at least one solar cell wafer on a first roll unit and conveying a metal foil to the first roll unit. The metal foil can be coupled to the solar cell wafer on the first roll unit to produce a unified pairing of the metal foil and the solar cell wafer. We disclose solar energy collection devices and manufacturing methods thereof enabling reduction of manufacturing costs due to simplification of the manufacturing process by a high throughput foil metallization process.
Trench process and structure for backside contact solar cells with polysilicon doped regions
A solar cell includes polysilicon P-type and N-type doped regions on a backside of a substrate, such as a silicon wafer. A trench structure separates the P-type doped region from the N-type doped region. Each of the P-type and N-type doped regions may be formed over a thin dielectric layer. The trench structure may include a textured surface for increased solar radiation collection. Among other advantages, the resulting structure increases efficiency by providing isolation between adjacent P-type and N-type doped regions, thereby preventing recombination in a space charge region where the doped regions would have touched.
Method for fabricating a solar module of rear contact solar cells using linear ribbon-type connector strips and respective solar module
A solar module and a method for fabricating a solar module comprising a plurality of rear contact solar cells are described. Rear contact solar cells (1) are provided with a large size of e.g. 156×156 mm.sup.2, Soldering pad arrangements (13, 15) applied on emitter contacts (5) and base contacts (7) are provided with one or more soldering pads (9, 11) arranged linearly. The soldering pad arrangements (13, 15) are arranged asymmetrically with respect to a longitudinal axis (17). Each solar cell (1) is then separated into first and second cell portions (19, 21) along a line (23) perpendicular to the longitudinal axis (17). Due to such cell separation and the asymmetrical design of the soldering pad arrangements (13, 15), the first and second cell portions (19, 21) may then be arranged alternately along a line with each second cell portion (21) arranged in a 180°-orientation with respect to the first cell portions (19) and such that emitter soldering pad arrangements (13) of a first cell portion (19) are aligned with base soldering pad arrangements (15) of neighboring second cell portions (21), and vice versa. Simple linear ribbon-type connector strips (25) may be used for interconnecting the cell portions (19, 21) by soldering onto the underlying aligned emitter and base soldering pad arrangements (13, 15). The interconnection approach enables using standard ribbon-type connector strips (25) while reducing any bow as well as reducing series resistance losses.
SINGLE-STEP METAL BOND AND CONTACT FORMATION FOR SOLAR CELLS
A method for fabricating a solar cell is disclosed. The method can include forming a dielectric region on a surface of a solar cell structure and forming a first metal layer on the dielectric region. The method can also include forming a second metal layer on the first metal layer and locally heating a particular region of the second metal layer, where heating includes forming a metal bond between the first and second metal layer and forming a contact between the first metal layer and the solar cell structure. The method can include forming an adhesive layer on the first metal layer and forming a second metal layer on the adhesive layer, where the adhesive layer mechanically couples the second metal layer to the first metal layer and allows for an electrical connection between the second metal layer to the first metal layer.
MONOLITHIC METAMORPHIC MULTI-JUNCTION SOLAR CELL
A monolithic metamorphic multi-junction solar cell comprising a first III-V subcell and a second III-V subcell and a third III-V subcell and a fourth Ge subcell, wherein the subcells are stacked on top of each other in the indicated order, and the first subcell forms the topmost subcell, and a metamorphic buffer is formed between the third subcell and the fourth subcell and all subcells each have an n-doped emitter layer and a p-doped base layer, and the emitter layer of the second subcell is greater than the base layer.
MONOLITHIC METAMORPHIC MULTI-JUNCTION SOLAR CELL
A monolithic metamorphic multi-junction solar cell comprising a first III-V subcell and a second III-V subcell and a third III-V subcell and a fourth Ge subcell, wherein the subcells are stacked on top of each other in the indicated order, and the first subcell forms the topmost subcell, and a metamorphic buffer is formed between the third subcell and the fourth subcell and all subcells each have an n-doped emitter layer and a p-doped base layer, and the emitter layer of the second subcell is greater than the base layer.
STACKED MONOLITHIC MULTIJUNCTION SOLAR CELL
A stacked monolithic multijunction solar cell, which includes a first subcell having a p-n junction with an emitter layer and a base layer, the thickness of the emitter layer being less than the thickness of the base layer at least by a factor of ten, and the first subcell comprising a substrate having a semiconductor material from the groups III and V or a substrate from the group IV, and which further includes a second subcell arranged on the first subcell and a third subcell arranged on the second subcell, the two subcells each including an emitter layer and a base layer, and a tunnel diode and a back side field layer each being formed between the subcells, the thickness of the emitter layer being greater than the thickness of the base layer in each case between the second subcell and in the third subcell.
Solar cell and solar cell module using the same
A solar cell and a solar cell module are disclosed. The solar cell module includes a plurality of solar cells each including a semiconductor substrate and first and second electrodes on the semiconductor substrate, the first and second electrodes being alternately positioned in a first direction and extended in a second direction intersecting the first direction, a first conductive line extended in the first direction to intersect the first and second electrodes, connected to the first electrode by a first conductive layer, and insulated from the second electrode by an insulating layer, and a second conductive line positioned in parallel with the first conductive line, connected to the second electrode by the first conductive layer, and insulated from the first electrode by the insulating layer.