A manufacturing method of a sensor chip package structure is provided. In the manufacturing method, a wafer including a plurality of sensor chips is provided, and each sensor chip has an active region and defines a pre-thinned region thereon. Each pre-thinned region is located at one side of the active region and covers a boundary line of each sensor chip. The pre-thinned region of each sensor chip is etched to form a concave portion. A redistribution layer is formed on the wafer. Subsequently, the wafer is cut to separate the sensor chips from one another, and each separated sensor chip has a wiring layer extending from the active region along a sidewall surface to a bottom surface of the concave portion. The separated sensor chips are respectively mounted on a plurality of substrates, and the active region is electrically connected to the substrate through the wiring layer.

A semiconductor structure includes a substrate, a plurality of micro semiconductor devices and a fixing structure. The micro semiconductor devices are disposed on the substrate. The fixing structure is disposed between the substrate and the micro semiconductor devices. The fixing structure includes a plurality of conductive layers and a plurality of supporting layers. The conductive layers are disposed on the lower surfaces of the micro semiconductor devices. The supporting layers are connected to the conductive layers and the substrate. The material of each of the conductive layers is different from the material of each of the supporting layers.

An optical device includes a substrate, a light receiving component, an encapsulant, a coupling layer and a light shielding layer. The light receiving component is disposed on the substrate. The encapsulant covers the light receiving component. The coupling layer is disposed on at least a portion of the encapsulant. The light shielding layer is disposed on the coupling layer.

The present invention provides a package structure of an optical apparatus which includes a substrate, a light emitting device, a light sensing device, and a light barrier member. The light emitting device is disposed on the substrate and electrically connected to the substrate. The light emitting device is for emitting light. The light sensing device is disposed on the substrate and is a chip scale package (CSP) device. The light sensing device is for receiving light reflected by an object. The light barrier member is disposed around a periphery of the light sensing device.

An imaging device includes: a photoelectric converter including first and second electrodes, and a photoelectric conversion layer located between the first electrode and the second electrode; a voltage supply circuit applying a bias voltage between the first electrode and the second electrode: an amplifier transistor including a gate electrically connected to the second electrode, the amplifier transistor configured to output a signal corresponding to a potential of the second electrode; and a detection circuit configured to detect a level of the signal from the amplifier transistor. The voltage supply circuit applies the bias voltage in a first voltage range when the level detected by the detection circuit is greater than or equal to a first threshold value, and applies the bias voltage in a second voltage range that is greater than the first voltage range when the level detected by the detection circuit is less than a second threshold value.

A manufacturing method of a sensor chip package structure is provided. In the manufacturing method, a wafer including a plurality of sensor chips is provided, and each sensor chip has an active region and defines a pre-thinned region thereon. Each pre-thinned region is located at one side of the active region and covers a boundary line of each sensor chip. The pre-thinned region of each sensor chip is etched to form a concave portion. A redistribution layer is formed on the wafer. Subsequently, the wafer is cut to separate the sensor chips from one another, and each separated sensor chip has a wiring layer extending from the active region along a sidewall surface to a bottom surface of the concave portion. The separated sensor chips are respectively mounted on a plurality of substrates, and the active region is electrically connected to the substrate through the wiring layer.

An optical device includes a substrate, a light receiving component, an encapsulant, a coupling layer and a light shielding layer. The light receiving component is disposed on the substrate. The encapsulant covers the light receiving component. The coupling layer is disposed on at least a portion of the encapsulant. The light shielding layer is disposed on the coupling layer.

Silicon-based or other electronic circuitry is dissolved or otherwise disabled by reactive materials within a semiconductor chip should the chip or a device containing the chip be subjected to tampering. Triggering circuits containing normally-OFF heterojunction field-effect photo-transistors are configured to cause reactions of the reactive materials within the chips upon exposure to light. The normally-OFF heterojunction field-effect photo-transistors can be fabricated during back-end-of-line processing through the use of polysilicon channel material, amorphous hydrogenated silicon gate contacts, hydrogenated crystalline silicon source/drain contacts, or other materials that allow processing at low temperatures.

A lead frame includes a main plate and a side plate. The main plate has a support portion and a projecting portion. The support portion has two opposite first sides and a support face located between the first sides. The projecting portion projects upward from one of the first sides in a direction opposite to the support face. The side plate is disposed separately from the one of the first sides of the support portion and is spaced apart from the projecting portion.

An optical sensor module and a sensor chip thereof are provided. The optical sensor module includes a substrate, a sensor chip and a passive chip. The sensor chip is disposed on the substrate, and the sensor chip includes a chip body having an active region located at a top side thereof and a recess portion depressed from a top surface of the chip body. The passive chip is accommodated in the recess portion, and a depth of the recess portion is greater than a thickness of the passive chip.