In at least one embodiment, the method is designed for producing a light-emitting diode display (1). The method comprises the following steps: A) providing a growth substrate (2); B) applying a buffer layer (4) directly or indirectly onto a substrate surface (20); C) producing a plurality of separate growth points (45) on or at the buffer layer (4); D) producing individual radiation-active islands (5), originating from the growth points (45), wherein the islands (5) each comprise an inorganic semiconductor layer sequence (50) with at least one active zone (55) and have a mean diameter, when viewed from above onto the substrate surface (20), between 50 nm and 20 m inclusive; and E) connecting the islands (5) to transistors (6) for electrically controlling the islands (5).

An AlGaN template including a substrate and an Al.sub.1-xGa.sub.xN crystallization thin film deposited on the substrate, where 0<x<1. A method for preparing the AlGaN template includes providing a substrate; and depositing an Al.sub.1-xGa.sub.xN crystallization thin film on the substrate.

A semiconductor wafer has, on one surface of a sapphire substrate, an element layer including an n-type layer, an active layer, and a p-type layer, and is characterized in that the surface of the element layer is bent in a convex way, and the curvature thereof is 530-800 km.sup.1.

A method of forming an electrical device that includes epitaxially growing a first conductivity type semiconductor material of a type III-V semiconductor on a semiconductor substrate. The first conductivity type semiconductor material continuously extending along an entirety of the semiconductor substrate in a plurality of triangular shaped islands; and conformally forming a layer of type III-V semiconductor material having a second conductivity type on the plurality of triangular shaped islands to provide a textured surface of a photovoltaic device. A light emitting diode is formed on the textured surface of the photovoltaic device.

Fabrication of a heterostructure, such as a group III nitride heterostructure, for use in an optoelectronic device is described. The heterostructure can be epitaxially grown on a sacrificial layer, which is located on a substrate structure. The sacrificial layer can be at least partially decomposed using a laser. The substrate structure can be completely removed from the heterostructure or remain attached thereto. One or more additional solutions for detaching the substrate structure from the heterostructure can be utilized. The heterostructure can undergo additional processing to form the optoelectronic device.

A graphene-based layer transfer (GBLT) technique is disclosed. In this approach, a device layer including a III-V semiconductor, Si, Ge, III-N semiconductor, SiC, SiGe, or II-VI semiconductor is fabricated on a graphene layer, which in turn is disposed on a substrate. The graphene layer or the substrate can be lattice-matched with the device layer to reduce defect in the device layer. The fabricated device layer is then removed from the substrate via, for example, a stressor attached to the device layer. In GBLT, the graphene layer serves as a reusable and universal platform for growing device layers and also serves a release layer that allows fast, precise, and repeatable release at the graphene surface.

A display device including a substrate and a plurality of pixels in a display region of the substrate. Each of the pixels includes first and second sub-pixels, and each of the first and second sub-pixels has a light emitting region for emitting light. The first sub-pixel includes a first light emitting element in the light emitting region and configured to emit visible light. The second sub-pixel includes a second light emitting element in the light emitting region and configured to emit infrared light and a light receiving element configured to receive the infrared light emitted from the second light emitting element to detect a user's touch. The second light emitting element and the light receiving element in the second sub-pixel are electrically insulated from and optically coupled to each other to form a photo-coupler.

A ScAlMgO.sub.4 single crystal substrate having less collapse of crystal orientation, and a method for producing the single crystal substrate. A ScAlMgO.sub.4 single crystal substrate is provided, wherein, when a center of the substrate is designated as coordinates (0,0) and a measurement beam width is set to 1 [mm]7 [mm] to conduct analysis according to an X-ray diffraction method at respective coordinate positions of (x.sub.m,0) to (x.sub.m,0) at an interval of 1 [mm] in an x-axis direction and (0,y.sub.n) to (0,y.sub.n) at an interval of 1 mm in a y-axis direction, wherein m and n are each an integer falling within the range so that the measurement beam is not stuck out from the substrate, a worst value of a full width at half maximum of a rocking curve at each of the coordinate positions is less than 20 [sec.].

A nitride semiconductor light-emitting element includes an n-type cladding layer including n-type AlGaN and having a first Al composition ratio, and a multiple quantum well layer in which a plurality (number N) of barrier layers including AlGaN having a second Al composition ratio more than the first Al composition ratio and a plural (number N) well layers having an Al composition ratio less than the second Al composition ratio are stacked alternately in this order, wherein the second Al composition ratio of the plurality of barrier layers of the multiple quantum well layer increases at a predetermined increase rate from an n-type cladding layer side toward an opposite side to the n-type cladding layer side.

A method of manufacturing semiconductor elements includes: disposing a semiconductor layer made of a nitride semiconductor on a first wafer; and bonding a second wafer to the first wafer via the semiconductor layer. The first wafer has an upper surface including a first region and a second region surrounding a periphery of the first region and located lower than the first region. In a top view of the first wafer, a first distance between an edge of the first wafer and the first region of the first wafer in each of a plurality of first directions parallel to respective m-axes of the semiconductor layer is smaller than a second distance between the edge of the first wafer and the first region of the first wafer in each of a plurality of second directions parallel to respective a-axes of the semiconductor layer.