H01L33/007

DISPLAY DEVICE

A display device includes: a substrate including a pixel; a scan line for supplying a scan signal to the pixel; a data line for supplying a data signal to the pixel; a first power line for supplying a first driving power source to the pixel; a second power line for supplying a second driving power source to the pixel; and a third power line for supplying a ground voltage to the pixel. The pixel includes: first and second electrodes spaced apart from each other on the substrate; a plurality of light emitting elements, each of the light emitting elements having first and second end portions in a length direction thereof and being arranged between the first electrode and the second electrode; and a first switch electrically connected between the third power line and the first electrode. The first switch is configured to be turned on by a control signal.

ALUMINUM NITRIDE LAMINATE MEMBER AND LIGHT-EMITTING DEVICE

There is provided an aluminum nitride laminate member including: a sapphire substrate having a base surface on which bumps are distributed periodically, each bump having a height of smaller than or equal to 500 nm; and an aluminum nitride layer grown on the base surface and having a flat surface, there being substantially no voids in the aluminum nitride layer.

Light emitting diode devices with zinc oxide layer

LED devices having high-quality single crystal ZnO structures for spreading currents and extracting light out of the LEDs are disclosed. In one aspect, a LED device is provided to include a substrate; a first semiconductor layer exhibiting a first conductivity type and formed over the substrate; an active light-emitting structure formed over the first semiconductor layer, the active light-emitting structure operable to emit light under electrical excitation; a second semiconductor layer exhibiting a second conductivity type and formed over the active light-emitting structure; and a single crystal ZnO structure formed over the second semiconductor layer and including a bottom single crystal ZnO portion over the second semiconductor layer and a top single crystal ZnO portion extending from the bottom single crystal ZnO portion, wherein the bottom single crystal ZnO portion is a contiguous single crystal ZnO portion without having voids.

Self-alignment process for micro light emitting diode using back-side exposure

Embodiments relate to a micro light-emitting-diode (LED) fabricated using a self-aligned process. To fabricate the LED, a metal layer is deposited on a p-type semiconductor. The p-type semiconductor is on an n-type semiconductor and the n-type semiconductor is on a top side of a substrate. The metal layer is patterned to define a p-metal. The p-type semiconductor is etched using the p-metal as an etch mask. Similarly, the n-type semiconductor is etched using the p-metal and the p-type semiconductor as an etch mask. A negative photoresist layer is deposited over the patterned p-metal and the p-type semiconductor. The negative photoresist is then exposed from the back side of the substrate, thus exposing the regions of the negative photoresist that are not masked by the p-metal. The negative photoresist is then developed to expose the p-metal.

Gallium nitride substrate and manufacturing method of nitride semiconductor crystal

The main purpose of the present invention is to provide: a nonpolar or semipolar GaN substrate, in which a nitride semiconductor crystal having a low stacking fault density can be epitaxially grown on the main surface of the substrate, and a technique required for the production of the substrate. This invention provides: a method for manufacturing an M-plane GaN substrate comprising; forming a mask pattern having a line-shaped opening parallel to an a-axis of a C-plane GaN substrate on an N-polar plane of the C-plane GaN substrate, growing a plane-shape GaN crystal of which thickness direction is an m-axis direction from the opening of the mask pattern by an ammonotharmal method, and cutting out the M-plane GaN substrate from the plane-shape GaN crystal.

Nitride semiconductor substrate and method for manufacturing same

A nitride semiconductor substrate includes a sapphire substrate and a nitride semiconductor layer formed thereon and containing a group III element including Al and nitrogen as a main component. A surface of the sapphire substrate where the nitride semiconductor layer is formed includes recesses having a maximum opening size of from 2 nm to 60 nm in an amount of from 110.sup.9 pieces to 110.sup.11 pieces per cm.sup.2. The recesses and surfaces immediately above the recesses form spaces. Of a surface of the nitride semiconductor layer on the sapphire substrate side, a height difference H between a surface immediately above of each recess and a surface in contact with a flat surface is 10 nm or less. A portion of the nitride semiconductor layer above each recess has a crystalline structure produced by growth along a polar plane of the group III element.

Monolithically integrated InGaN/GaN quantum nanowire devices

InGaN/GaN quantum layer nanowire light emitting diodes are fabricated into a single cluster capable of exhibiting a wide spectral output range. The nanowires having InGaN/GaN quantum layers formed of quantum dots are tuned to different output wavelengths using different nanowire diameters, for example, to achieve a full spectral output range covering the entire visible spectrum for display applications. The entire cluster is formed using a monolithically integrated fabrication technique that employs a single-step selective area epitaxy growth.

GALLIUM NITRIDE MATERIALS AND METHODS

The invention provides semiconductor materials including a gallium nitride material layer formed on a silicon substrate and methods to form the semiconductor materials. The semiconductor materials include a transition layer formed between the silicon substrate and the gallium nitride material layer. The transition layer is compositionally-graded to lower stresses in the gallium nitride material layer which can result from differences in thermal expansion rates between the gallium nitride material and the substrate. The lowering of stresses in the gallium nitride material layer reduces the tendency of cracks to form. Thus, the invention enables the production of semiconductor materials including gallium nitride material layers having few or no cracks. The semiconductor materials may be used in a number of microelectronic and optical applications.

Methods For Using Remote Plasma Chemical Vapor Deposition (RP-CVD) And Sputtering Deposition To Grow Layers In Light Emitting Devices

Described herein are methods for using remote plasma chemical vapor deposition (RP-CVD) and sputtering deposition to grow layers for light emitting devices. A method includes growing a light emitting device structure on a growth substrate, and growing a tunnel junction on the light emitting device structure using at least one of RP-CVD and sputtering deposition. The tunnel junction includes a p++ layer in direct contact with a p-type region, where the p++ layer is grown by using at least one of RP-CVD and sputtering deposition. Another method for growing a device includes growing a p-type region over a growth substrate using at least one of RP-CVD and sputtering deposition, and growing further layers over the p-type region. Another method for growing a device includes growing a light emitting region and an n-type region using at least one of RP-CVD and sputtering deposition over a p-type region.

METHOD OF PRODUCING A RADIATION-EMITTING SEMICONDUCTOR CHIP AND RADIATION-EMITTING SEMICONDUCTOR CHIP

A method of producing a radiation-emitting semiconductor chip includes providing a growth substrate, epitaxially growing a buffer layer on the growth substrate such that a plurality of V-pits is generated in the buffer layer, epitaxially growing a radiation-generating active semiconductor layer sequence on the buffer layer, wherein the structure of the V-pits continues into the active semiconductor layer sequence, epitaxially growing a further layer sequence on the active semiconductor layer sequence, wherein the structure of the V-pits continues into the further layer sequence, selectively removing the further layer sequence from facets of the V-pits, wherein the further layer sequence remains on a main surface of the active semiconductor layer sequence, and epitaxially growing a p-doped semiconductor layer that completely or partially fills the V-pits.