Oxygen controlled PVD AlN buffers for GaN-based optoelectronic and electronic devices is described. Methods of forming a PVD AlN buffer for GaN-based optoelectronic and electronic devices in an oxygen controlled manner are also described. In an example, a method of forming an aluminum nitride (AlN) buffer layer for GaN-based optoelectronic or electronic devices involves reactive sputtering an AlN layer above a substrate, the reactive sputtering involving reacting an aluminum-containing target housed in a physical vapor deposition (PVD) chamber with a nitrogen-containing gas or a plasma based on a nitrogen-containing gas. The method further involves incorporating oxygen into the AlN layer.

Disclosed is a method for fabricating an LED module. The method includes: constructing a chip-on-carrier including a chip retainer having a horizontal bonding plane and a plurality of LED chips in which electrode pads are bonded to the bonding plane of the chip retainer; and transferring the plurality of LED chips in a predetermined arrangement from the chip retainer to a substrate by transfer printing. The transfer printing includes: primarily section-wise exposing a transfer tape to reduce the adhesive strength of the transfer tape such that bonding areas are formed at predetermined intervals on the transfer tape; and pressurizing the transfer tape against the LED chips on the chip retainer to attach the LED chips to the corresponding bonding areas of the transfer tape and detaching the electrode pads of the LED chips from the chip retainer to pick up the chips.

There is provided a nitride semiconductor template, including: a substrate having a front surface and a back surface opposite to the front surface; a back side semiconductor layer provided on a back surface side of the substrate, comprising a polycrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient of the substrate; and a front side semiconductor layer provided on a front surface side of the substrate, comprising a monocrystalline group III nitride semiconductor, and having a linear expansion coefficient different from a linear expansion coefficient of the substrate, wherein a thickness of the front side semiconductor layer is a thickness exceeding a critical thickness at which cracks are generated in the front side semiconductor layer when only the front side semiconductor layer is formed without forming the back side semiconductor layer.

A method of manufacturing a light-emitting element includes: forming a plurality of rod-shaped layered structures by performing steps including: forming a first conductive-type semiconductor layer on a substrate, forming, on the first conductive-type semiconductor layer, an insulating film defining a plurality of openings and a plurality of rods of a first conductive-type semiconductor, wherein each of the rods is disposed through a respective one of the plurality of openings, forming a light-emitting layer covering outer surfaces of the plurality of rods, and forming a second conductive-type semiconductor layer covering outer surfaces of the light-emitting layer; forming a photoresist pattern covering a portion of the plurality of the rod-shaped layered structures; removing a portion of the insulating film in a region that is not covered by the photoresist pattern; and removing a portion of the plurality of rod-shaped layered structures in the region that is not covered by the photoresist pattern.

A micro-light emitting diode (LED) includes an epitaxial structure having a mesa and a top portion on the mesa. The epitaxial structure further includes quantum wells within the mesa configured to emit light, claddings surrounding the quantum wells, and a light emitting surface on a side opposite the mesa and top portion. A reflective contact is on the top portion of the epitaxial structure. Light emitted from the quantum wells are transmitted through the mesa and the top portion in first directions, and reflected by the reflective contact back through the top portion and the mesa in second directions toward the light emitting surface. The top portion allows the quantum wells to be positioned at a parabola focal point of the mesa without limiting cladding thickness.

Methods for fabricating semiconductor devices incorporating an activated p-(Al,In)GaN layer include exposing a p-(Al,In)GaN layer to a gaseous composition of H.sub.2 and/or NH.sub.3 under conditions that would otherwise passivate the p-(Al,In)GaN layer. The methods do not include subjecting the p-(Al,In)GaN layer to a separate activation step in a low hydrogen or hydrogen-free environment. The methods can be used to fabricate buried activated n/p-(Al,In)GaN tunnel junctions, which can be incorporated into electronic devices.

A light emitting device includes a substrate, a light emitting unit disposed on the substrate, a metallic electrode unit, a metallic adhesion layer disposed on the first and second electrodes of the electrode unit, and a protective layer disposed on the adhesion layer. The first electrode is disposed on a portion of a first-type semiconductor layer of the light emitting unit. The second electrode is disposed on a second-type semiconductor layer of the light emitting unit disposed on a separated portion of the first-type semiconductor layer. The first and second electrodes are partially exposed by the protective layer and the adhesion layer that is partially exposed by the protective layer. A production method for the light emitting device is also disclosed.

A method for manufacturing a display panel comprising light emitting device including micro LEDs includes providing multiple donor wafers having a surface region and forming an epitaxial material overlying the surface region. The epitaxial material includes an n-type region, an active region comprising at least one light emitting layer overlying the n-type region, and a p-type region overlying the active layer region. The multiple donor wafers are configured to emit different color emissions. The epitaxial material on the multiple donor wafers is patterned to form a plurality of dice, characterized by a first pitch between a pair of dice less than a design width. At least some of the dice are selectively transferred from the multiple donor wafers to a common carrier wafer such that the carrier wafer is configured with different color emitting LEDs. The different color LEDs could comprise red-green-blue LEDs to form a RGB display panel.

Direct-bonded LED arrays and applications are provided. An example process fabricates a LED structure that includes coplanar electrical contacts for p-type and n-type semiconductors of the LED structure on a flat bonding interface surface of the LED structure. The coplanar electrical contacts of the flat bonding interface surface are direct-bonded to electrical contacts of a driver circuit for the LED structure. In a wafer-level process, micro-LED structures are fabricated on a first wafer, including coplanar electrical contacts for p-type and n-type semiconductors of the LED structures on the flat bonding interface surfaces of the wafer. At least the coplanar electrical contacts of the flat bonding interface are direct-bonded to electrical contacts of CMOS driver circuits on a second wafer. The process provides a transparent and flexible micro-LED array display, with each micro-LED structure having an illumination area approximately the size of a pixel or a smallest controllable element of an image represented on a high-resolution video display.

Semiconductor structures formed with annealing for use in the fabrication of optoelectronic devices. The semiconductor structures can include a substrate, a nucleation layer and a buffer layer. The nucleation layer and the buffer layer can be epitaxially grown and then annealed. The temperature of the annealing of the nucleation layer and the buffer layer is greater than the temperature of the epitaxial growth of the layers. The annealing reduces the dislocation density in any subsequent layers that are added to the semiconductor structures. A desorption minimizing layer epitaxially grown on the buffer layer can be used to minimize desorption during the annealing of the layer which also aids in curtailing dislocation density and cracks in the semiconductor structures.