A method of manufacturing a substrate with reduced threading dislocation density is disclosed, which comprises: (i) at a first temperature, forming a first layer of wafer material on a semiconductor substrate, the first layer arranged to be doped with a first concentration of at least one dopant that is different to the wafer material; and (ii) at a second temperature higher than the first temperature, forming a second layer of the wafer material on the first layer to obtain the substrate, the second layer arranged to be doped with a progressively decreasing concentration of the dopant during formation, the doping configured to be decreased from the first concentration to a second concentration. The wafer material and dopant are different to silicon. A related substrate is also disclosed.

The invention relates to a method for manufacturing an optoelectronic device (1), comprising the following steps: a) providing a growth substrate (10) made from a semiconductor material; b) forming a plurality of diodes (20) each comprising a lower face (20i); c) removing at least a portion (12; 13) of the substrate so as to free the lower face (20i); wherein: step a) involves producing a lower part and an upper part of the substrate, the upper part (12) having a uniform thickness (e.sub.ref) and a level of doping less than that of the lower part; step c) involving removal of the lower part (11) by selective chemical etching with respect to the upper part (12).

A flip-chip light emitting diode element capable of reducing lateral resistance. The flip-chip light emitting diode element includes a stacked body structure configured by sequentially stacking a first n-type group III nitride semiconductor layer having a carrier concentration that is at least 110.sup.19 cm.sup.3 but less than 310.sup.20 cm.sup.3, a second n-type group III nitride semiconductor layer having a carrier concentration that is at least 510.sup.17 cm.sup.3 but less than 110.sup.19 cm.sup.3, a light-emitting layer formed by a group III nitride semiconductor, and a p-type group III nitride semiconductor layer. A height of unevenness on an interface between the first n-type group III nitride semiconductor layer and the second n-type group III nitride semiconductor layer is greater than that of unevenness of an interface between the second n-type group III nitride semiconductor layer and the light emitting layer.

An optoelectronic semiconductor device and a method for manufacturing an optoelectronic semiconductor device are disclosed. In an embodiment an optoelectronic semiconductor device includes a semiconductor body comprising a first region of a first conductive type, an active region, a second region of a second conductive type and a coupling-out surface, wherein the first region, the active region and the second region are arranged along a stacking direction, wherein the active region extends from a rear surface opposite the coupling-out surface to the coupling-out surface along a longitudinal direction transverse to or perpendicular to the stacking direction, wherein the coupling-out surface is arranged plane-parallel to the rear surface, and wherein the coupling-out surface and the rear surface of the semiconductor body are produced by an etching process.

A nitride semiconductor template includes a heterogeneous substrate, a first nitride semiconductor layer that is formed on one surface of the heterogeneous substrate, includes a nitride semiconductor and has an in-plane thickness variation of not more than 4.0%, and a second nitride semiconductor layer that is formed on an annular region including an outer periphery of an other surface of the heterogeneous substrate, includes the nitride semiconductor and has a thickness of not less than 1 m.

A method for producing an optoelectronic semiconductor chip is disclosed. A substrate is provided and a first layer is grown. An etching process is carrying out to initiate V-defects. A second layer is grown and a quantum film structure is grown. An optoelectronic semiconductor chip is also disclosed. The method can be used to produce the optoelectronic semiconductor chip.

A micro LED display panel and a manufacturing method thereof are provided. The micro LED display panel includes: a substrate, a plurality of micro LEDs disposed on the substrate and arranged in an array, a transparent encapsulation layer covering the plurality of micro LEDs, and a quantum dot (QD) layer disposed on the encapsulation layer. By adding the QD layer on the encapsulation layer, the short wavelength light emitted by the micro LEDs excites the QD layer to emit light, so that the micro LEDs and the QD layer form the basic display units of the micro LED display panel to expand the gamut of micro LED display panel and improve display quality of the micro LED display panel.

An optoelectronic device comprising a semiconductor structure includes a p-type active region and an n-type active region. The semiconductor structure is comprised solely of one or more superlattices, where each superlattice is comprised of a plurality of unit cells. Each unit cell comprises at least two distinct substantially single crystal layers.

The invention relates to a method for producing a nitride semiconductor component (100), comprising the steps of: providing a growth substrate (1) having a growth surface (10) formed from a planar area (11) with a plurality of three-dimensionally shaped surface structures (12) on said planar area (11), growing a nitride-based semiconductor layer sequence (30) on the growth surface (10), growth beginning selectively on a growth area (13) of said growth substrate, and the growth area (13) being less than 45% of the growth surface (10). The invention also relates to a nitride semiconductor component (100) which can be produced according to said method.

There are provided a Group III nitride semiconductor light-emitting device having complicated irregularities on the light extraction surface. The light-emitting device comprises a substrate, a p-type semiconductor layer, a light-emitting layer, and an n-type semiconductor layer. The light-emitting device has protrusions extending upward from the surface of the n-type semiconductor layer on the n-type semiconductor layer. Each protrusion has a wall portion disposed so as to intersect with the surface of the n-type semiconductor layer. The wall portion has a first surface facing the n-type semiconductor layer. An angle between the first surface and the n-type semiconductor layer is 10 to 85.