A manufacturing method of a semiconductor element includes forming a plurality of islands, each including a semiconductor layer containing a nitride semiconductor and a support formed on the semiconductor layer, on a sapphire substrate, joining the support to a retention substrate via an adhesive member, peeling off the semiconductor layer from the sapphire substrate by irradiating the semiconductor layer with laser light, and polishing a surface of the semiconductor layers peeled off from the sapphire substrate.

A manufacturing method of a semiconductor element includes forming a plurality of semiconductor layers on a sapphire substrate, each of the semiconductor layers having a first surface on the sapphire substrate side and a second surface on the opposite side, joining the second surfaces of the plurality of semiconductor layers to a retention member via an adhesive member, peeling off the plurality of semiconductor layers from the sapphire substrate by irradiating the first surfaces of the plurality of semiconductor layers with laser light, and polishing the first surfaces of the plurality of semiconductor layers. At least one semiconductor layer among the plurality of semiconductor layers includes a polishing indication part extending from the second surface toward the first surface. The polishing is executed until the polishing indication part is exposed to the polished surface.

An epitaxial structure of a semiconductor light-emitting element includes an n-type layer, a V-pit control layer, a light-emitting layer, and a p-type layer stacked from bottom to top. The light-emitting layer includes a plurality of well layers and a plurality of barrier layers stacked alternately. The V-pit control layer includes a first superlattice layer, and a distance between a bottom surface of the V-pit control layer and a bottom surface of the first superlattice layer is less than or equal to 0.15 ?m. The bottom surface of the first superlattice layer and a bottom surface of the light-emitting layer have a distance therebetween ranging from 0.05 ?m to 0.3 ?m, and each of the first superlattice layer and the light-emitting layer is an Indium (In)-containing layer. A semiconductor light-emitting element and a light-emitting device are also provided.

Exemplary semiconductor structures may include a plurality of LED structures and a backplane layer. Exemplary semiconductor structures may also include a light barrier region positioned between the LED structures and the backplane layer. The light barrier region may be operable to absorb light at wavelengths shorter than or about 300 nm and transmit light at wavelengths greater than or about 350.

A device including an activated p-type layer comprising a III-Nitride based Mg-doped layer grown by vapor phase deposition or a growth method different from MBE. The p-type layer is activated through a sidewall of the p-type layer after the removal of defects from the sidewall thereby increasing a hole concentration in the p-type layer. In one or more examples, the device includes an active region between a first n-type layer and the p-type layer; a second n-type layer on the p-type layer; and a tunnel junction between the second n-type layer and the p-type layer, and the activated p-type layer has a hole concentration characterized by a current density of at least 100 Amps per centimeter square flowing between the first n-type layer and the second n-type layer in response to a voltage of 4 volts or less applied across the first n-type layer and the second n-type layer.

A template substrate includes: a main substrate including an edge (E), a peripheral portion including the edge, and a non-peripheral portion located on the inner side of the peripheral portion; and a mask pattern located above the main substrate. The mask pattern includes a mask portion, a plurality of first opening portions (KF) each having a width direction as a first direction and a longitudinal direction as a second direction and overlapping the non-peripheral portion in plan view, and one or more second opening portions (KB) arranged along the edge in plan view.

A semiconductor wafer includes a substrate (1), a buffer layer (2) deposited on the substrate (1), and an epitaxial layer (4) above the buffer layer (2). The buffer layer (2) includes a plurality of semiconductor material layers (22) and a plurality of oxygen-doped material layers (21). The semiconductor material layers (22) and the oxygen-doped material layers (21) are deposited in an alternating arrangement on top of each other. Oxygen concentrations of the oxygen-doped material layers (21) gradually decrease along a direction from the substrate (1) to the epitaxial layer (4).

Micro light-emitting diode (LED) display fabrication and assembly are described. In an example, a micro-light emitting diode (LED) display panel includes a display backplane substrate having a plurality of metal bumps thereon. A plurality of LED pixel elements includes ones of LED pixel elements bonded to corresponding ones of the plurality of metal bumps of display backplane substrate. One or more of the plurality of LED pixel elements has a graphene layer thereon. The graphene layer is on a side of the one or more of the plurality of LED pixel elements opposite the side of the metal bumps.

A method for manufacturing a semiconductor device includes: preparing a wafer including sapphire, the wafer having an upper surface that includes a first region and a second region, the second region surrounding the first region and located at a position at least 2 m higher or lower than the first region; and forming a semiconductor layer at the upper surface, the semiconductor layer including at least one layer that comprises Al.sub.zGa.sub.1-zN (0.03z0.15).

A process for producing a light emitting diode device, the process including: forming a plurality of quantum dots on a surface of a layer including a first area and a second area; exposing the first area of the surface to light having a first wavelength while exposing the first area to a first etchant that causes the quantum dots in the first area to be etched at a first etch rate while the quantum dots have a dimension at or greater than a first threshold dimension; exposing the second area of the surface to light having a second wavelength while exposing the second area to a second etchant that causes the quantum dots in the second area to be etched at a third etch rate while the quantum dots have a dimension at or greater than a second threshold dimension; and processing the etched layer to form the LED device.