This disclosure discloses a light-emitting element having a light-emitting unit, a transparent layer and a wavelength conversion layer formed on the transparent layer. The transparent layer covers the light-emitting unit. The wavelength conversion layer includes a phosphor layer having a phosphor and a stress release layer without the phosphor.

A method of forming semiconductor nanorods includes: placing, in a chamber, a masking material and a base comprising a semiconductor, wherein an etching rate of the masking material in a chemical reaction with a reactant gas during dry etching is lower than an etching rate of a semiconductor in a chemical reaction with the reactant gas during dry etching; and performing dry-etching to form a plurality of dot-masks, each having a form of a dot containing the masking material, on a surface of the semiconductor and to remove a portion of the semiconductor exposed from the dot-masks, wherein the dry-etching is performed under a pressure in the chamber in a predetermined range that allows the masking material scattered by the etching to be adhered to a surface of the semiconductor with a predetermined size of the dots and a predetermined density of the dots.

A method for manufacturing a micro-LED display screen includes: forming an N-type GaN layer, a quantum-well light-emitting layer, and a P-type GaN layer on a sapphire substrate sequentially; etching the P-type GaN layer, the quantum-well light-emitting layer, and the N-type GaN layer from top to bottom, to form a first trench; forming an ITO layer on the surface of the P-type GaN layer, and etching the ITO layer to form a second trench; generating an N-type contact electrode in the first trench; generating a reflective electrode having a longitudinal cross-section in a shape with a wide upper side and a narrow lower side, respectively, on an upper surface of the N-type contact electrode and in the second trench; depositing an insulating layer on a surface of the micro-LED chip, and etching the insulating layer to expose the reflective electrodes; and soldering a driving circuit substrate to the reflective electrode.

To provide a light-emitting diode in which cracking or peeling of interlayer insulating film is suppressed. The first interlayer insulating film is continuously formed in a film on a DBR layer, a first p-electrode, and a first n-electrode. The first interlayer insulating film is a multilayer formed by alternately depositing a SiO.sub.2 layer and a TiO.sub.2 layer, and the number of layers is eleven. The SiO.sub.2 layer is formed of a material having a property of generating compressive stress. When the light-emitting diode according to the first embodiment is exposed to a high temperature, the TiO.sub.2 layer in the first interlayer insulating film changes its property from generating compressive stress to generating tensile stress. The tensile stress by the TiO.sub.2 layer and the compressive stress by the SiO.sub.2 layer counteract each other. As a result, the internal stress of the first interlayer insulating film is relaxed.

An image display device includes a plurality of micro light-emission elements that constitute a pixel and that are provided on a driving circuit substrate. The micro light-emission element displays an image by emitting light to a side opposite to the driving circuit substrate. A light convergence portion that converges light is disposed in the pixel.

A growth layer having a growth surface with protruding domains is described. The protruding domains can be separated by a substantially flat growth surface located between the protruding domains. A protruding domain can include an internal region that can be filled with a gas and/or can be partially or completely filled with one or more materials that differ from the material of the growth layer, which forms an outer surface of each of the protruding domains.

A semiconductor light emitting device including a substrate, an electrode and a light emitting region is provided. The substrate may have protruding portions formed in a repeating pattern on substantially an entire surface of the substrate while the rest of the surface may be substantially flat. The cross sections of the protruding portions taken along planes orthogonal to the surface of the substrate may be semi-circular in shape. The cross sections of the protruding portions may in alternative be convex in shape. A buffer layer and a GaN layer may be formed on the substrate.

The present invention discloses a light emitting element and a fabrication method thereof. The light emitting element includes: an anode electrode, a hole transport layer, a light emitting layer, an electron transport layer and a cathode electrode, all of the light emitting units are divided into a plurality of light emitting sets, each light emitting set includes at least two light emitting units and the light emitting units in a same light emitting set share a same electron transport layer and a same cathode electrode. In the technical solutions of the present invention, all of the light emitting units in a same light emitting set share a same electron transport layer and a same cathode electrode, thus effectively reducing the number of the cathode electrodes.

A method for producing a semiconductor chip (100) is provided, in which, during a growth process for growing a first semiconductor layer (1), an inhomogeneous lateral temperature distribution is created along at least one direction of extent of the growing first semiconductor layer (1), such that a lateral variation of a material composition of the first semiconductor layer (1) is produced. A semiconductor chip (100) is additionally provided.

An optoelectronic device includes a semiconductor stack, including a first semiconductor layer, an active layer formed on the first semiconductor layer, and a second semiconductor layer; a first metal layer formed on a top surface of the second semiconductor layer; a second metal layer formed on a top surface of the first semiconductor layer; an insulative layer formed on the top surface of the first semiconductor layer and the top surface of the second semiconductor layer; wherein a space between a sidewall of the first metal layer and a sidewall of the semiconductor stack is less than 3 m.