Method for manufacturing micro-LEDs comprising the following steps: i) providing a stack comprising at least one strongly n-doped GaN layer (104), an n-doped GaN layer (105), quantum wells (106) and a p-doped GaN layer (107), ii) porosifying the GaN layer (104), to obtain a porosified GaN layer (104), iii) forming mesas in the stack, iv) covering the porosified GaN layer (104) with a second electrode (301) or with an encapsulation layer (302), the second electrode (301) or the encapsulation layer (302) being in direct contact with the porosified GaN layer (104). step ii) being carried out so that the optical index of the porosified GaN layer (104) does not vary by more than 10% with respect to the optical index of the second electrode (301) and/or with respect to the optical index of the encapsulation layer (302).

A semiconductor device includes a substrate having an upper surface, a buffer layer formed on the upper surface, and an element structure formed on the buffer layer. The substrate includes a plurality of holes extending from the upper surface of the substrate to an inside of the substrate and forming a plurality of openings at the upper surface of the substrate. In a cross-sectional view of the semiconductor device, at least two of the holes have different depths.

An optoelectronic device having a stack including an alternation of at least one semiconductor layer of a first material and of semiconductor layers of a second material, each layer of the first material being sandwiched between two layers of the second material and defining a quantum well, wherein the first material is an inorganic perovskite material, and the second material is an inorganic semiconductor material.

A semiconductor light emitting element and a manufacture method thereof are provided. The semiconductor light emitting element includes: a substrate, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer being arranged sequentially from bottom to top, and further includes a surface plasmon excition layer being arranged on the p-type semiconductor layer and a surface plasmon excited layer being arranged between the quantum well layer and the p-type semiconductor layer, or the surface plasmon excitation layer being arranged between the p-type semiconductor layer and the surface plasmon excitation layer, or the surface plasmon excitation layers being arranged respectively between the quantum well layer and the p-type semiconductor layer and between the p-type semiconductor layer and the surface plasmon excitation layer. The quantum efficiency of the semiconductor light emitting element is improved, the light emitting uniformity and the anti-ESD capability of the semiconductor light emitting element are enhanced.

In an embodiment a radiation-emitting semiconductor chip includes a first doped region, an active region adjacent to the first doped region and a second doped region arranged on a side of the active region facing away from the first doped region, wherein the first doped region is structured in a step-like manner and includes several planes in a direction perpendicular to a main extension plane of the semiconductor chip, and wherein the active region covers the first doped region on a side surface and a top surface.

A method of manufacturing an electronic device comprising the following successive steps: a) forming a structure comprising a diode stack disposed on a first substrate, and a sacrificial layer of semiconductor material interposed between the first substrate and the diode stack; b) transferring the structure to a second substrate; and c) removing the first substrate by electropolishing the sacrificial layer by applying a bias voltage to the sacrificial layer via the diode stack.

A device may include a metal contact between a first isolation region and a second isolation region on a first surface of an epitaxial layer. The device may include a first sidewall and a second sidewall on a second surface of the epitaxial layer distal to the first isolation region and the second isolation region. The device may include a wavelength converting layer on the epitaxial layer between the first sidewall and the second sidewall.

A method for fabricating small size light emitting diodes (LEDs) on high-quality epitaxial crystal layers. III-nitride epitaxial lateral overgrowth (ELO) layers are grown on a substrate using a growth restrict mask. III-nitride device layers are grown on wings of the III-nitride ELO layers, to form island-like III-nitride semiconductor layers. The wings of the III-nitride ELO layers have at least an order of magnitude smaller defect density than the substrate, resulting in superior characteristics for the devices made thereon. Light emitting mesas are etched from the island-like III-nitride semiconductor layers, wherein each of the light emitting mesas corresponds to a device; and a device unit pattern is etched from the island-like III-nitride semiconductor layers, wherein the device unit pattern is comprised of one or more of the light emitting mesas. The device unit pattern including the island-like III-nitride semiconductor layers is then transferred to display panel or a carrier.

A multilayer film structure includes a SiC substrate and a film disposed on the SiC substrate and containing a nitride-based material at least containing Ga, wherein the multilayer film structure has an off-angle of 0.03? or more and 8? or less with respect to a Silicon face of a (0001) plane of a SiC single crystal forming the SiC substrate and the film containing the nitride-based material has a C content of 2?10.sup.19 atoms/cm.sup.3 or less and a Cl content of 2?10.sup.18 atoms/cm.sup.3 or less.

A process for producing at least two adjacent regions, each comprising an array of light-emitting wires connected together in a given region by a transparent conductive layer, comprises: producing, on a substrate, a plurality of individual zones for growing wires extending over an area greater than the cumulative area of the two chips; growing wires in the individual growth zones; removing wires from at least one zone forming an initial free area to define the arrays of wires, the initial free area comprising individual growth zones level with the removed wires; and depositing a transparent conductive layer on each array of wires to electrically connect the wires of a given array of wires, each conductive layer being separated from the conductive layer of the neighbouring region by a free area. A device obtained using the process of the invention is also provided.