An InGaN-based LED epitaxial wafer and a fabrication method thereof are disclosed, wherein the InGaN-based LED epitaxial wafer includes: a substrate; an InGaN layer, formed on a surface of the substrate, having an In content between 40% and 90%, so as to ensure that the LED epitaxial wafer is capable of emitting long-wavelength light or near-infrared rays; a p-type metal oxide layer, formed on a surface of the InGaN layer facing away from the substrate, acting as a hole injection layer for the InGaN layer.

Disclosed are a composite substrate, an epitaxial wafer, and a semiconductor device. The composite substrate includes: a support substrate layer; a first alumina layer disposed on the support substrate layer; and a sapphire substrate layer disposed on the first alumina layer. The first alumina layer may increase a bonding force between the sapphire substrate layer and the support substrate layer and release a stress between the sapphire substrate layer and the support substrate layer. Meanwhile, the existence of the first alumina layer may improve a breakdown voltage of a material without increasing a thickness of the sapphire substrate layer.

Method for porosifying mesas comprising the following steps: providing a structure (100) comprising a substrate (110) covered with (Al,In,Ga)N/(Al,In,Ga)N mesas (120), the substrate (110) comprising a support layer (114), a first layer of non-doped GaN (111) and a second layer of doped GaN (112), the mesas (120) comprising a third layer of heavily doped (Al,In,Ga)N(123) and a fourth layer of non-doped or lightly doped (Al,In,Ga)N(124), a part (112b) of the second layer (112) of doped GaN being extended in the mesas (120) or a part (123a) of the third layer (123) of heavily doped (Al,In,Ga)N being extended in the base substrate (110), immersing the structure (100) and a counter-electrode in an electrolytic solution, applying a voltage or a current between the structure (100) and the counter-electrode so as to porosify the third layer (123) of heavily doped (Al,In,Ga)N of the mesas (120).

A method for forming a matrix of light-emitting diode (LED) elements (11, 21, 31) of different colours is provided. The method comprises epitaxially growing, on a GaN sacrificial layer (140), a first n-doped GaN layer (111), a first In.sub.xGa.sub.(1-X)N layer (112) and a first p-doped GaN layer (113) to form a first array of first LED elements (11) for emitting light of a first colour, and forming a first etch mask (151) comprising a plurality of first trenches (161). The method further comprises: epitaxially growing a second array of second LED elements (21), for emitting light of a second colour, in the plurality of first trenches; forming a second etch mask (152) protecting the second array and comprising a plurality of second trenches (162); and epitaxially growing a third array of third LED elements (31), for emitting light of a third colour, in the plurality of second trenches.

A method for manufacturing a growth substrate, including producing mesas based on GaN having various porosification levels, implementing differentiated steps of electrochemical porosification, non-photoassisted and photoassisted, of various portions of the mesas.

A light emitting diode including a side reflection layer. The light emitting diode includes: a semiconductor stack and a light exit surface having a roughened surface through which light generated from an active layer is emitted; side surfaces defining the light exit surface; and a side reflection layer covering at least part of the side surfaces. The light exit surface is disposed over a first conductivity type semiconductor layer opposite to the ohmic reflection layer, all layers from the active layer to the light exit surface are formed of gallium nitride-based semiconductors, and a distance from the active layer to the light exit surface is 50 ?m or more.

The present application provides a manufacturing method for a high-voltage LED chip. The sapphire substrate PSS in the embodiments of the present application has a double-layer structure with an upper layer and a lower layer, the upper layer being silicon oxide (SiO.sub.2), and the lower layer being sapphire Al.sub.2O.sub.3. Before making the sapphire Al.sub.2O.sub.3 patterned, a layer of silicon oxide (SiO.sub.2) is deposited on the sapphire Al.sub.2O.sub.3, and then the sapphire substrate PSS is made by dry etching, and the substrate is used to fabricate the high-voltage LED chip. After etching and bridging the isolation groove by the inductively coupled plasma ICP, the sapphire substrate PSS is corroded. The silicon oxide (SiO.sub.2) above the sapphire Al.sub.2O.sub.3 is removed. A flat platform is formed at the isolation groove of the high-voltage LED chip, which is convenient to subsequently cover the bridging metal, thereby solving the problems such as bridging metal fractures.

A method of fabricating a semiconductor light emitting device includes forming a first conductivity type semiconductor layer, forming an active layer by alternately forming a plurality of quantum well layers and a plurality of quantum barrier layers on the first conductivity type semiconductor layer, and forming a second conductivity type semiconductor layer on the active layer. The plurality of quantum barrier layers include at least one first quantum barrier layer adjacent to the first conductivity type semiconductor layer and at least one second quantum barrier layer adjacent to the second conductivity type semiconductor layer. The forming of the active layer includes allowing the at least one first quantum barrier layer to be grown at a first temperature and allowing the at least one second quantum barrier layer to be grown at a second temperature lower than the first temperature.

A device includes a substrate (10) and a III-nitride structure (15) grown on the substrate, the III-nitride structure comprising a light emitting layer (16) disposed between an n-type region (14) and a p-type region (18). The substrate is a RA0.sub.3 (MO).sub.n where R is one of a trivalent cation: Sc, In, Y and a lanthanide; A is one of a trivalent cation: Fe (III), Ga and Al; M is one for a divalent cation: Mg, Mn, Fe (II), Co, Cu, Zn and Cd; and n is an integer1. The substrate has an inplane lattice constant a.sub.substrate. At lease one III-nitride layer in the III-nitride structure has a bulk lattice constant a.sub.layer such that [(|a.sub.substratea.sub.layer|)/a.sub.substrate]*100% is no more than 1%.

An RAMO.sub.4 substrate that includes an RAMO.sub.4 monocrystalline substrate formed of a single crystal represented by general formula RAMO.sub.4, wherein R represents one or more trivalent elements selected from the group consisting of Sc, In, Y, and lanthanoid elements, A represents one or more trivalent elements selected from the group consisting of Fe(III), Ga, and Al, and M represents one or more divalent elements selected from the group consisting of Mg, Mn, Fe(II), Co, Cu, Zn, and Cd. The RAMO.sub.4 monocrystalline substrate has a principal surface with a plurality of grooves. The principal surface has an off-angle with respect to a cleaving surface of the single crystal. The RAMO.sub.4 monocrystalline substrate satisfies tan Wy/Wx, where Wx is the width at the top surface of a raised portion between the grooves, and Wy is the height of the raised portion.