A semiconductor chip of a LED and a manufacturing method thereof are disclosed. The semiconductor chip includes a substrate, an N-type semiconductor layer, an active region, a P-type semiconductor layer, and at least one semiconductor exposing portion extending from the P-type semiconductor layer to the N-type semiconductor layer. The semiconductor chip further includes one or more current blocking layers, a transparent conductive layer, an N-type electrode, and a P-type electrode, wherein the current blocking layer encapsulates the P-type semiconductor in such a manner to be stacked on the P-type semiconductor layer. The transparent conductive layer has one or more through holes corresponding to the one or more current blocking layers respectively. The N-type electrode is stacked on the N-type semiconductor layer and the P-type electrode is stacked on the N-type semiconductor layer. The P-type prongs of the P-type electrode are retained in the through holes of the transparent conductive layer respectively.

A semiconductor body and a method for producing a semiconductor body are disclosed. In an embodiment a semiconductor body includes a p-conducting region, wherein the p-conducting region has at least one barrier zone and a contact zone, wherein the barrier zone has a first magnesium concentration and a first aluminum concentration, wherein the contact zone has a second magnesium concentration and a second aluminum concentration, wherein the first aluminum concentration is greater than the second aluminum concentration, wherein the first magnesium concentration is at least ten times less than the second magnesium concentration, wherein the contact zone forms an outwardly exposed surface of the semiconductor body, and wherein the barrier zone adjoins the contact zone, and wherein the semiconductor body is based on a nitride compound semiconductor material.

A method for forming a laterally-grown group III metal nitride crystal includes providing a substrate, the substrate including one of sapphire, silicon carbide, gallium arsenide, silicon, germanium, a silicon-germanium alloy, MgAl.sub.2O.sub.4 spinel, ZnO, ZrB.sub.2, BP, InP, AlON, ScAlMgO.sub.4, YFeZnO.sub.4, MgO, Fe.sub.2NiO.sub.4, LiGa.sub.5O.sub.8, Na.sub.2MoO.sub.4, Na.sub.2WO.sub.4, In.sub.2CdO.sub.4, lithium aluminate (LiAlO.sub.2), LiGaO.sub.2, Ca.sub.8La.sub.2(PO.sub.4).sub.6O.sub.2, gallium nitride, or aluminum nitride (AlN), forming a pattern on the substrate, the pattern comprising growth centers having a minimum dimension between 1 micrometer and 100 micrometers, and being characterized by at least one pitch dimension between 20 micrometers and 5 millimeters, growing a group III metal nitride from the pattern of growth centers vertically and laterally, and removing the laterally-grown group III metal nitride layer from the substrate. A laterally-grown group III metal nitride layer coalesces, leaving an air gap between the laterally-grown group III metal nitride layer and the substrate or a mask thereupon.

A method of forming and testing a plurality of monolithic electronic devices is provided. As part of the method a monolithic device array comprising Group III-nitrides is formed on a sacrificial substrate. A test substrate comprising electrical contacts is aligned with electrical contacts of the monolithic device array and bonded to the monolithic device array via bonding dielectric layers. Power is supplied from the test substrate to test the monolithic devices of the monolithic device array. Portions of the sacrificial substrate are then selectively removed to separate each of the monolithic electronic devices, wherein a sacrificial dielectric layer is removed to separate each monolithic electronic device from the test substrate.

Various examples are provided related to InGaN-relaxed templates. In one example, a device structure includes a GaN layer; and a semibulk template comprising a plurality of stacked periods on the GaN layer. Each period can include a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of a top period of the stacked periods is greater than a thickness of the GaN interlayer of a bottom period disposed on the GaN layer. In another example, a method includes forming a GaN layer and forming a semibulk template including a plurality of stacked periods on the GaN layer. Each period can include a layer of InGaN and a GaN interlayer disposed on the layer of InGaN, where a thickness of the GaN interlayer of the top period is greater than the GaN interlayer of the bottom period.

Two, standard dimension, Si wafers, one <111>-oriented and the other <100>-oriented for example, are bonded together to form a two-ply substrate. Such an Si double-wafer substrate is stiffer than either a double-thickness <111>-oriented or <100>-oriented wafer. C-beveling on the two constituent wafers results in a B-bevel edge of the two-ply substrate that does not create stress risers. Also, standard thickness wafers are commercially available. GaN epitaxial layer is then grown on this two-ply substrate.

A light emitting device including a first LED stack, a second LED stack disposed on the first LED stack, a third LED stack disposed on the second LED stack, and a common electrode electrically connected to a first conductivity type semiconductor layer of each of the first, second, and third LED stacks, in which the common electrode includes a step in at least one of the first, second and third LED stacks.

A display device according to an embodiment of the disclosure may include a substrate including a display area including a plurality of pixel areas each having an emission area and a non-display area surrounding at least one side of the display area, and a pixel provided in each of the pixel areas and including display element part. The display element part may include a first insulating layer disposed on the substrate, at least one light emitting element disposed on the first insulating layer and each having a first end and a second end in a longitudinal direction, a first layer disposed on the first insulating layer and the light emitting element and being in contact with a first area of each of the first and second ends of the light emitting element, a second layer disposed on the light emitting element and being in contact with a second area of each of the first and second ends of the light emitting element, and an interlayer insulating layer provided between the first layer and the second layer. Here, the first layer and the second layer may include a semiconductor material.

A method for manufacturing a semiconductor element includes: providing a wafer comprising first and second regions at an upper surface of the wafer, the second region being located at a periphery of the first region and being at a lower position than the first region; and forming a semiconductor layer made of a nitride semiconductor at the upper surface of the wafer. In a top-view, the first region comprises an extension portion at an end portion of the first region in a first direction that passes through the center of the wafer parallel to an m-axis of the semiconductor layer, the extension portion extending in a direction from a center of the wafer toward an edge of the wafer or in a direction from an edge of the wafer toward a center of the wafer.

A method for forming a light emitting diode (LED) uses aluminum-based material layers and oxidation during the LED formation. In some embodiments, the method may include forming an n-type layer of the LED on a substrate, forming at least one sidewall restriction layer of the LED on the substrate with the sidewall restriction layer comprising an aluminum-based material, forming a quantum well layer of the LED on the substrate, forming a p-type layer of the LED on the substrate, exposing the substrate to water vapor, and heating the substrate to oxidize at least an outer portion of the electron blocking layer. The aluminum-based material may include aluminum indium nitride or aluminum gallium arsenide.