A method of manufacturing a wafer includes a wafer preparing step of preparing a wafer including a plurality of semiconductor devices joined to a substrate by respective adhesive layers, a determining step of determining whether each of the semiconductor devices joined to the substrate is defective or non-defective, a laser beam applying step of applying a laser beam to heat one of the adhesive layers by which one of the semiconductor devices that has been determined as defective is bonded to the substrate, thereby melting the adhesive layer in an area of the wafer that is irradiated with the laser beam, and a treating step of treating the semiconductor device released from a bonded state due to the adhesive layer being melted in the laser beam applying step.

A high temperature optoelectronic isolator for power electronics operating above 250 degrees Celcius.

A light-emitting element includes a core including a first semiconductor layer including a first portion and a second portion, the first and second portions having side surfaces at different inclinations, a second semiconductor layer disposed on the first semiconductor layer, and an emissive layer disposed between the first semiconductor layer and the second semiconductor layer; a first insulating layer surrounding the first portion of the first semiconductor layer; and a second insulating layer surrounding the second portion of the first semiconductor layer.

A method of manufacturing a semiconductor element according to the present disclosure includes an element forming step (S1) of forming, on an underlying substrate (11), a semiconductor element (15) connected to the underlying substrate (11) via a connecting portion (13b) and including an upper surface (15a) inclined with respect to a growth surface of the underlying substrate (11), a preparing step (S2) of preparing a support substrate (16) including an opposing surface (16c) facing the underlying substrate (11), a bonding step (S3) of pressing the upper surface (15a) of the semiconductor element (15) against the opposing surface (16c) of the support substrate (16) and heating the upper surface (15a) to bond the upper surface (15a) of the semiconductor element (15) to the support substrate (16), and a peeling step (S4) of peeling the semiconductor element (15) from the underlying substrate (11).

Described are light emitting diode (LED) devices comprising a mesa with semiconductor layers, the semiconductor layers including an N-type layer, an active layer, and a P-type layer. The mesa has a top surface and at least one side wall, the at least one side wall defining a trench having a bottom surface. A passivation layer is on the at least one side wall and on the top surface of the mesa, the passivation layer comprises one or more a low-refractive index material and distributed Bragg reflector (DBR). A p-type contact is on the top surface of the mesa, and an n-type contact on the bottom surface of the trench.

A light emitting element includes a first semiconductor layer including a first type of semiconductor, the first semiconductor layer including a 1-1-th semiconductor layer and a 1-2-th semiconductor layer, which are arranged in a length direction of the light emitting element; a second semiconductor layer including a second type of semiconductor different from the first type; an active layer disposed between the 1-2-th semiconductor layer and the second semiconductor layer; and an intermediate layer disposed between the 1-1-th semiconductor layer and the 1-2-th semiconductor layer and having a porous structure.

A method for growing on a substrate strongly aligned uniform cross-section semiconductor composite nanocolumns is disclosed. The method includes: (a) forming faceted pyramidal pits on the substrate surface; (b) initiating nucleation on the facets of the pits; and; (c) promoting the growth of nuclei toward the center of the pits where they coalesce with twinning and grow afterwards together as composite nanocolumns. Multi-quantum-well, core-shell nanocolumn heterostructures can be grown on the sidewalls of the nanocolumns. Furthermore, a continuous semiconductor epitaxial layer can be formed through the overgrowth of the nanocolumns to facilitate fabrication of high-quality planar device structures or for light emitting structures.

A semiconductor light emitting element includes: an n-type clad layer of an n-type aluminum gallium nitride (AlGaN)-based semiconductor material; an active layer of an AlGaN-based semiconductor material provided on a first top surface of the n-type clad layer; and an n-side electrode provided on a second top surface of the n-type clad layer adjacent to the first top surface. The n-side electrode includes a first metal layer on the second top surface containing titanium (Ti) and a second metal layer on the first metal layer containing aluminum (Al). A root-mean-square roughness (Rq) of a top surface of the second metal layer is 5 nm or less.

A semiconductor light-emitting element includes a substrate having a first surface, a plurality of protrusions disposed, with spacing opened between one another, on the first surface, a buffer layer disposed to cover the plurality of protrusions and the first surface positioned between the plurality of protrusions, a dimension of the buffer layer in a first direction orthogonal to the first surface being smaller than a dimension in the first direction of each of the plurality of protrusions, an n-type semiconductor layer that is disposed on the buffer layer and is doped with an n-type impurity, an active layer disposed on the n-type semiconductor layer, and a p-type semiconductor layer that is disposed on the active layer and is doped with a p-type impurity.

In an embodiment an optoelectronic semiconductor chip includes a semiconductor layer sequence with a first layer, a second layer and an active layer arranged between the first layer and the second layer, the semiconductor layer sequence having at least one injection region, wherein the first layer includes a first conductivity type, wherein the second layer includes a second conductivity type, wherein the semiconductor layer sequence includes the first conductivity type within the entire injection region, wherein the injection region, starting from the first layer, at least partially penetrates the active layer, wherein side surfaces of the semiconductor layer sequence are formed at least in places by the injection region, and wherein the injection region is configured to inject charge carriers directly into the active layer.