A method for manufacturing a gallium nitride film includes the steps of placing a substrate so as to face a target containing nitrogen and gallium in a vacuum chamber, supplying a sputtering gas into the vacuum chamber, supplying a nitrogen radical into the vacuum chamber, generating a plasma of the sputtering gas by application of a voltage to the target, generating a gallium ion by a collision of an ion of the sputtering gas with the target, and stopping the application of the voltage to the target and depositing gallium nitride on the substrate. The gallium nitride is generated by a reaction of the gallium ion with a nitrogen anion which is generated by a reaction of an electron in the vacuum chamber with the nitrogen radical.

A wafer includes a buried substrate; a first layer of silicon (100) disposed on the buried substrate that includes silicon sidewalls (111) at an angle to the buried substrate and that form a bottom of each of multiple U-shaped grooves; a second layer of patterned oxide disposed on the silicon (100) that provides vertical sidewalls of each U-shaped groove formed within the first and second layers; a third layer of a buffer covering the first layer and partially covering the second layer partway up the vertical sidewalls; and multiple gallium nitride (GaN)-based structures disposed within the multiple U-shaped grooves, the multiple GaN-based structures each including cubic gallium nitride (c-GaN) formed at merged growth fronts of hexagonal gallium nitride (h-GaN) that extend from the silicon sidewalls (111).

A light emitting device having first, second and third dimensions that are orthogonal may include a light emitting semiconductor device configured to emit light via a first surface in a plane formed by the first and second dimensions. The light emitting device may further include a wavelength converting structure disposed on the first surface of the light emitting semiconductor device, the wavelength converting structure extending beyond the light emitting semiconductor device in the first dimension and the light emitting semiconductor device extending beyond the wavelength converting structure in the second dimension. The light emitting device may further include one or more optical extraction features in at least one gap formed by the wavelength converting structure extending beyond the light emitting semiconductor structure in the first dimension and/or formed by the light emitting semiconductor structure extending beyond the wavelength converting structure in the second dimension.

The present disclosure describes epitaxial oxide high electron mobility transistors (HEMTs). In some embodiments, a HEMT comprises: a substrate; a template layer on the substrate; a first epitaxial semiconductor layer on the template layer; and a second epitaxial semiconductor layer on the first epitaxial semiconductor layer. The template layer can comprise crystalline metallic Al(111). The first epitaxial semiconductor layer can comprise (Al.sub.xGa.sub.1-x).sub.yO.sub.z, wherein 0≤x≤1, 1≤y≤3, and 2≤z≤4, wherein the (Al.sub.xGa.sub.1-x).sub.yO.sub.z comprises a Pna21 space group, and wherein the (Al.sub.xGa.sub.1-x)O.sub.z comprises a first conductivity type formed via polarization. The second epitaxial semiconductor layer can comprise a second oxide material.

The present disclosure describes methods and epitaxial oxide devices with impact ionization. A method can comprise: applying a bias across a semiconductor structure using a first electrical contact and a second electrical contact; injecting a hot electron, from the first electrical contact, through a second semiconductor layer, and into a conduction band of a first epitaxial oxide material; and forming an excess electron-hole pair in an impact ionization region of the first semiconductor layer via impact ionization. The semiconductor structure can comprise: the first electrical contact; the first semiconductor layer with the first epitaxial oxide material with a first bandgap coupled to the first electrical contact; a second semiconductor layer with a second epitaxial oxide material with a second bandgap coupled to the first semiconductor layer; and a second electrical contact coupled to the second semiconductor layer, wherein the second bandgap is wider than the first bandgap.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, including: a substrate; a first epitaxial oxide layer comprising (Ni.sub.x1Mg.sub.y1Zn.sub.1-x1-y1)(Al.sub.q1Ga.sub.1-q1).sub.2O.sub.4 wherein 0≤x1≤1, 0≤y1≤1 and 0≤q1≤1; and a second epitaxial oxide layer comprising (Ni.sub.x2Mg.sub.y2Zn.sub.1-x2-y2)(Al.sub.q2Ga.sub.1-q2).sub.2O.sub.4 wherein 0≤x2≤1, 0≤y2≤1 and 0≤q2≤1. In some cases, at least one condition selected from x1≠x2, y1≠y2, and q1≠q2 is satisfied.

The present disclosure describes epitaxial oxide devices with impact ionization. In some embodiments, a semiconductor device comprises: a first semiconductor layer; a second semiconductor layer coupled to the first semiconductor layer; and a first and a second electrical contact coupled to the second and first semiconductor layers, respectively. The first semiconductor layer can comprise a first epitaxial oxide material with a first bandgap and an impact ionization region. The second semiconductor layer can comprise a second epitaxial oxide material with a second bandgap that is wider than the first bandgap.

A process for the production of a layer structure of a nitride semiconductor component on a silicon surface, comprising: provision of a substrate having a silicon surface; deposition of an aluminium-containing nitride nucleation layer on the silicon surface of the substrate; optional: deposition of an aluminium-containing nitride buffer layer on the nitride nucleation layer; deposition of a masking layer on the nitride nucleation layer or, if present, on the first nitride buffer layer; deposition of a gallium-containing first nitride semiconductor layer on the masking layer, wherein the masking layer is deposited in such a way that, in the deposition step of the first nitride semiconductor layer, initially separate crystallites grow that coalesce above a coalescence layer thickness and occupy an average surface area of at least 0.16 μm.sup.2 in a layer plane of the coalesced nitride semiconductor layer that is perpendicular to the growth direction.

The present disclosure provides techniques for epitaxial oxide materials, structures and devices. In some embodiments, a semiconductor structure includes an epitaxial oxide heterostructure, comprising: a substrate; a first epitaxial oxide layer comprising Li(Al.sub.x1Ga.sub.1−x1)O.sub.2 wherein 0≤x1≤1; and a second epitaxial oxide layer comprising (Al.sub.x2Ga.sub.1−x2).sub.2O.sub.3 wherein 0≤x2≤1.

The present disclosure provides a combined epitaxial growth system having multiple reaction chambers, an operation method, a device, and a manufactured chip and an application thereof. With a special metal-organic chemical vapor deposition (MOCVD) machine, a group III-V compound epi-wafer and a group II-VI compound epi-wafer are sequentially grown on a substrate. A time interval a at which multiple group III-V compound reaction chambers are sequentially started is the same as growth time y of the group II-VI compound epi-wafer. With the multi-chamber and stepwise manner, not only are a group III-V compound and a group II-VI compound deposited in the reaction chambers more effectively, but the time division multiplexing (TDM), effective integration of the stepwise process, and capacity matching are also implemented. The present disclosure further provides a combined epitaxial growth device having multiple reaction chambers, including a first growth device, a feeding device and a second growth device.