A semiconductor heterostructure for an optoelectronic device is disclosed. The semiconductor heterostructure includes at least one stress control layer within a plurality of semiconductor layers used in the optoelectronic device. Each stress control layer includes stress control regions separated from adjacent stress control regions by a predetermined spacing. The stress control layer induces one of a tensile stress and a compressive stress in an adjacent semiconductor layer.

A method of manufacturing electronic devices, including the successive steps of: a) growing, on a surface of a first substrate, a stack including at least one semiconductor layer; b) bonding a second substrate on a surface of the stack opposite to the first substrate, and then removing the first substrate; c) bonding a third substrate to a surface of the stack opposite to the second substrate, and then removing the second substrate; d) cutting the assembly including the third substrate and the stack into a plurality of first chips each including a portion of the stack; and e) bonding each first chip, by its surface opposite to the third substrate, to a surface of a fourth semiconductor substrate inside and on top of which a plurality of integrated control circuits have been previously formed.

A method for forming a semiconductor device comprising a graded wurtzite III-nitride alloy layer, including a wurtzite III-nitride alloy, on a second layer. A polarization doping concentration profile is selected for the graded wurtzite III-nitride alloy layer based on an intended function of the semiconductor device. Based on the selected polarization doping concentration profile for the graded wurtzite III-nitride alloy layer, a composition-polarization change rate of the graded wurtzite III-nitride alloy layer and a grading speed of the graded wurtzite III-nitride alloy layer are determined. The composition-polarization change rate and grading speed are based on a composition of first and second elements of the wurtzite III-nitride alloy. The graded wurtzite III-nitride alloy layer is formed on the second layer having the selected polarization doping concentration profile using the determined composition-polarization change rate and grading speed to adjust the composition of the first and second III-nitride elements of the wurtzite III-nitride alloy based on a current position in the graded wurtzite III-nitride alloy layer from the second layer.

A semiconductor chip of a LED and a manufacturing method thereof are disclosed. The semiconductor chip includes a substrate, an N-type semiconductor layer, an active region, a P-type semiconductor layer, and at least one semiconductor exposing portion extending from the P-type semiconductor layer to the N-type semiconductor layer. The semiconductor chip further includes one or more current blocking layers, a transparent conductive layer, an N-type electrode, and a P-type electrode, wherein the current blocking layer encapsulates the P-type semiconductor in such a manner to be stacked on the P-type semiconductor layer. The transparent conductive layer has one or more through holes corresponding to the one or more current blocking layers respectively. The N-type electrode is stacked on the N-type semiconductor layer and the P-type electrode is stacked on the N-type semiconductor layer. The P-type prongs of the P-type electrode are retained in the through holes of the transparent conductive layer respectively.

A method for manufacturing a light-emitting diode is provided, including the following steps in succession, while maintaining a substrate in a vapour-phase epitaxial growth chamber: epitaxial deposition, with an atmosphere having a first non-zero concentration of ammonia in the chamber, of a first GaN alloy layer P-doped with magnesium; epitaxial deposition, on the first GaN alloy layer, of a sacrificial GaN alloy layer in a second atmosphere in the chamber that is not supplied with magnesium; placing the second atmosphere inside the chamber under conditions with a second concentration of ammonia that is at least equal to a third of the first non-zero concentration so as to remove the sacrificial GaN layer; and then epitaxial deposition of a second N-type doped GaN alloy layer so as to form a tunnel junction with the first GaN alloy layer.

A light emitting device includes a substrate; a pattern of a plurality of protrusions protruding from the substrate; a first semiconductor layer provided on the substrate; an active layer provided on the first semiconductor layer; and a second semiconductor layer provided on the active layer, in which each of the protrusions includes a first layer formed integrally with the substrate and protruding from an upper surface of the base substrate; and a second layer provided on the first layer and formed of a material different from that of the first layer.

The present invention provides light-emitting devices with improved quantum efficiency. The light emitting diode structure comprising: a p-doped layer an n-doped layer; and a multiple quantum well structure sandwiched between the p-doped layer and n-doped layer, wherein the multiple quantum well structure comprising a quantum well disposed between n-doped barrier layers.

A device comprising a semiconductor layer including a plurality of compositional inhomogeneous regions is provided. The difference between an average band gap for the plurality of compositional inhomogeneous regions and an average band gap for a remaining portion of the semiconductor layer can be at least thermal energy. Additionally, a characteristic size of the plurality of compositional inhomogeneous regions can be smaller than an inverse of a dislocation density for the semiconductor layer.

A polarization field assisted DUV-LED including a bottom substrate and a n-contact/injection layer formed on the bottom substrate. The n-contact/injection layer includes: a first region for accommodating strain relaxation; a second region for lateral access with a low sheet resistance and higher conductivity compared to the first region to minimize resistive losses and heat generation; and a third region of a graded vertical injection layer with low vertical resistance to minimize heat loss due to vertical resistance. The DUV-LED also includes a p-contact region, and an emitting active region between the n-contact/injection layer and the p-contact region. The injection of electrons and holes into quantum wells proceeds due to tunneling of electrons and holes under the barriers due to less than 2 nm thickness of barriers. This carrier injection lowers the Turn ON voltage of LEDs and reduces heat generation.

An optical device wafer processing method for transferring an optical device layer of an optical device wafer onto a transfer member includes: a dividing groove forming step of forming dividing grooves in a buffer layer; a transfer member joining step of joining the transfer member to a front surface of the optical device layer; and a laser beam applying step of applying a pulsed laser beam from a back surface side of a crystalline substrate. In the laser beam applying step, the buffer layer, or the buffer layer and part of the optical device layer, left without being divided in the dividing groove forming step, are modified in nature.