H01L2221/1047

Airgap formation in BEOL interconnect structure using sidewall image transfer

A method and structure of forming air gaps with a sidewall image transfer process such as self-aligned double patterning to reduce capacitances. Different materials can be provided in the mandrel and non-mandrel regions to enlarge a process window for metal line end formation.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a substrate, at least one first gate structure, at least one first spacer, at least one source drain structure, and a conductive plug. The first gate structure is present on the substrate. The first spacer is present on at least one sidewall of the first gate structure. The source drain structure is present adjacent to the first spacer. The conductive plug is electrically connected to the source drain structure while leaving a gap between the conductive plug and the spacer.

AIRGAP VERTICAL TRANSISTOR WITHOUT STRUCTURAL COLLAPSE
20200395238 · 2020-12-17 ·

Embodiments of the present invention are directed to forming an airgap-based vertical field effect transistor (VFET) without structural collapse. A dielectric collar anchors the structure while forming the airgaps. In a non-limiting embodiment of the invention, a vertical transistor is formed over a substrate. The vertical transistor can include a fin, a top spacer, a top source/drain (S/D) on the fin, and a contact on the top S/D. A dielectric layer is recessed below a top surface of the top spacer and a dielectric collar is formed on the recessed surface of the dielectric layer. Portions of the dielectric layer are removed to form a first cavity and a second cavity. A first airgap is formed in the first cavity and a second airgap is formed in the second cavity. The dielectric collar anchors the top S/D to the top spacer while forming the first airgap and the second airgap.

Porogen bonded gap filling material in semiconductor manufacturing

A device includes a substrate; a first layer over the substrate, the first layer containing a metallic material, wherein the first layer includes a trench; and a porous material layer having a first portion and a second portion. The first portion is disposed in the trench. The second portion is disposed on a top surface of the first layer. The first and the second portions contain substantially same percentage of Si, substantially same percentage of O, and substantially same percentage of C.

SEMICONDUCTOR DEVICE INCLUDING A POROUS DIELECTRIC LAYER, AND METHOD OF FORMING THE SEMICONDUCTOR DEVICE

A semiconductor device includes a porous dielectric layer including a recessed portion, a conductive layer formed in the recessed portion, and a cap layer formed on the porous dielectric layer and on the conductive layer in the recessed portion, an upper surface of the porous dielectric layer being exposed through a gap in the cap layer.

BOTTOM-UP CURING OF DIELECTRIC FILMS IN INTEGRATED CIRCUITS

Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a passive energy source formed from a conductive metal. A dielectric target layer is formed over the first energy source. An active energy source is used to generate electromagnetic radiation having a predetermined wavelength, wherein the dielectric target layer is substantially transparent to the electromagnetic radiation at the predetermined wavelength. The dielectric target layer is exposed to the electromagnetic radiation by transmitting the electromagnetic radiation into and through the dielectric target layer to impact the passive energy source. The passive energy source is configured to, based at least in part on being exposed to the electromagnetic radiation, absorb the electromagnetic radiation, experience a conductive material temperature increase such that the conductive material generates heat energy, and emit the generated heat energy to the dielectric target layer.

ION IMPLANTATION ASSISTED CURING FOR FLOWABLE POROUS DIELECTRICS

Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes a forming a first IC layer above the substrate, wherein the first IC layer includes a network of interconnect structures, wherein the network of interconnect structures is configured to communicatively couple electronic devices of the IC. A second IC layer is formed over the first IC layer. The second IC layer is implanted with a predetermined ion implantation dose, maintained at a predetermined temperature, and further exposed to electromagnetic radiation from an energy source. The second IC layer is configured to, based at least in part of being exposed to the ion implantation and the electromagnetic radiation, experience changes in the chemical composition of the second IC layer and transform the second IC layer.

Interconnect structure and method

A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.

Remote plasma based deposition of oxygen doped silicon carbide films
10832904 · 2020-11-10 · ·

Disclosed are methods and systems for providing oxygen doped silicon carbide. A layer of oxygen doped silicon carbide can be provided under process conditions that employ one or more silicon-containing precursors that have one or more silicon-hydrogen bonds and/or silicon-silicon bonds. The silicon-containing precursors may also have one or more silicon-oxygen bonds and/or silicon-carbon bonds. One or more radical species in a substantially low energy state can react with the silicon-containing precursors to form the oxygen doped silicon carbide film. The one or more radical species can be formed in a remote plasma source.

System and Method of Forming a Porous Low-K Structure
20200303184 · 2020-09-24 ·

The present disclosure involves forming a porous low-k dielectric structure. A plurality of conductive elements is formed over the substrate. The conductive elements are separated from one another by a plurality of openings. A barrier layer is formed over the conductive elements. The barrier layer is formed to cover sidewalls of the openings. A treatment process is performed to the barrier layer. The barrier layer becomes hydrophilic after the treatment process is performed. A dielectric material is formed over the barrier layer after the treatment process has been performed. The dielectric material fills the openings and contains a plurality of porogens.