An aluminum interconnection apparatus comprises a metal structure formed over a substrate, wherein the metal structure is formed of a copper and aluminum alloy, a first alloy layer formed underneath the metal structure and a first barrier layer formed underneath the first alloy layer, wherein the first barrier layer is generated by a reaction between the first alloy layer and an adjacent dielectric layer during a thermal process.

A device includes a substrate and at least one electrically conducting portion supported by the substrate, the at least one electrically conducting portion including a signal line and a ground plane electrically isolated from the signal line. The electrically conducting portion includes a layer of a first electrically conducting material and a layer of a metal oxide material including anodic aluminum oxide (AAO) and one or more nanowires (NW) of a second electrically conducting material each formed within a corresponding pore extending through the AAO from a first side of the layer to a second side of the layer of the metal oxide material opposite the first side.

An interconnection structure fabrication method is provided. The method includes providing a substrate; forming a conductive film with a first thickness and having a first lattice structure and a first grain size, wherein the first thickness is greater than the first grain size; and performing an annealing process to change the first lattice structure of the conductive film to a second lattice structure and to change the first grain size to a second grain size. The second grain size is greater than the first grain size, and the first thickness is greater than or equal to the second grain size. The method also includes etching portion of the conductive film to form at least one conductive layer; etching portion of the conductive layer to form at least one trench having a depth smaller than the first thickness in the conductive layer to form an electrical interconnection wire and conductive vias; and forming a dielectric layer covering the substrate, sidewalls of the conductive layer, and the trench.

A graphene-clad metal interconnect extends material properties of graphene to both damascene and patterned interconnect structures at lower metal layers, leading to significant reductions in resistance. Graphene cladding can be used with or without a metal barrier/liner. Presence of a barrier/liner can serve to catalyze growth of an overlying graphene layer. Graphene may also be selectively grown on barrier surfaces. Fully integrated structures and process flows for integrated circuits with graphene-clad metallization are described.

IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

A semiconductor device includes: a lower structure including a device and a lower wiring structure; an insulating layer on the lower structure; a via penetrating the insulating layer; a wiring pattern on the insulating layer and the via; and a silicon oxide layer covering the wiring pattern, and including hydrogen, wherein the wiring pattern includes first and second conductive layers, an upper surface protective layer, and a side surface protective layer, wherein the second conductive layer is on the first conductive layer, wherein the upper surface protective layer covers an upper surface of the second conductive layer, and the side surface protective layer covers side surfaces of the first and second conductive layers, and wherein each of the upper surface protective layer and the side surface protective layer includes a metal material having an activation energy higher than that of a metal material of the second conductive layer.