An SiC semiconductor device includes an SiC semiconductor layer including an SiC monocrystal that is constituted of a hexagonal crystal and having a first main surface as a device surface facing a c-plane of the SiC monocrystal and has an off angle inclined with respect to the c-plane, a second main surface at a side opposite to the first main surface, and a side surface facing an a-plane of the SiC monocrystal and has an angle less than the off angle with respect to a normal to the first main surface when the normal is 0°.

A laser processing device includes: a light source configured to output laser light; a space light modulator for modulating the laser light output from the light source in accordance with a modulation pattern and outputting the modulated laser light; a converging lens for converging the laser light output from the space light modulator to an object, and forming a converging spot on the object; a movement unit for relatively moving the converging spot with respect to the object; and a control unit for relatively moving, while setting a position of the converging spot in a Z direction intersecting with an incident surface of the laser light on the object at a first Z position, the converging spot along a line extended in an X direction along the incident surface by controlling at least the space light modulator and the movement unit.

A semiconductor device has a semiconductor wafer including a plurality of semiconductor die and a plurality of contact pads formed over a first surface of the semiconductor wafer. A trench is formed partially through the first surface of the semiconductor wafer. An insulating material is disposed over the first surface of the semiconductor wafer and into the trench. A conductive layer is formed over the contact pads. The conductive layer can be printed to extend over the insulating material in the trench between adjacent contact pads. A portion of the semiconductor wafer opposite the first surface of the semiconductor wafer is removed to the insulating material in the trench. An insulating layer is formed over a second surface of the semiconductor wafer and side surfaces of the semiconductor wafer. The semiconductor wafer is singulated through the insulating material in the first trench to separate the semiconductor die.

Methods of manufacturing a semiconductor package structure are provided. A method includes: bonding dies and dummy dies to a wafer; forming a dielectric material layer on the wafer to cover the dies and the dummy dies; performing a first planarization process to remove a first portion of the dielectric material layer over top surfaces of the dies and the dummy dies; and performing a second planarization process to remove portions of the dies, portions of the dummy dies and a second portion of the dielectric material layer, and a dielectric layer is formed laterally aside the dies and the dummy dies; wherein after the second planarization process is performed, a total thickness variation of the dies is less than a total thickness variation of the dummy dies.

In an embodiment, an apparatus includes an energy source, a support platform for holding a wafer, an optical path extending from the energy source to the support platform, and a photomask aligned such that a patterned major surface of the photomask is parallel to the force of gravity, where the optical path passes through the photomask, where the patterned major surface of the photomask is perpendicular to a topmost surface of the support platform.

A semiconductor assembly includes a first die and a second die. The semiconductor assembly also includes a film on die (FOD) layer configured to attach the first die to the second die. The FOD layer is disposed on a first surface of the first die. The FOD layer includes a first portion comprising a first die attach film (DAF) disposed on an inner region of the first surface. The FOD layer also includes a second portion that includes a second DAF disposed on a peripheral region of the first surface surrounding the inner region. The second DAF includes a different material than the first DAF.

A semiconductor package is provided. The semiconductor package includes: semiconductor dies, separated from one another, and including die I/Os at their active sides; and a redistribution structure, disposed at the active sides of the semiconductor dies and connected to the die I/Os, wherein the redistribution structure includes first and second routing layers sequentially arranged along a direction away from the die I/Os, the first routing layer includes a ground plane and first signal lines laterally surrounded by and isolated from the first ground plane, the first signal lines connect to the die I/Os and rout the die I/Os from a central region to a peripheral region of the redistribution structure, the second routing layer includes second signal lines and ground lines, and the second signal lines and the ground lines respectively extend from a location in the peripheral region to another location in the peripheral region through the central region.

A template for growing Group III-nitride semiconductor layers, a Group III-nitride semiconductor light emitting device and methods of manufacturing the same are provided. The template for growing Group III-nitride semiconductor layers includes a growth substrate having a first plane, a second plane opposite to the first plane and a groove extending inwards the growth substrate from the first plane, an insert for heat dissipation placed and secured in the groove, and a nucleation layer formed on a partially removed portion of the first plane.

A semiconductor package includes a package substrate, an interposer provided on the package substrate, a plurality of semiconductor devices on the interposer and spaced apart from each other, and electrically connected to each other through the interposer, at least one dummy member on the interposer to cover at least one corner portion of the interposer and arranged spaced apart from a first semiconductor device among the plurality of semiconductor devices, and a sealing member contacting the interposer and filling a space between the first semiconductor device and the at least one dummy member so as to cover a first side surface of the first semiconductor device, a first side surface of the at least one dummy member, and an upper surface of the dummy member. A second side surface, opposite to the first side surface, of the at least one dummy member is uncovered by the sealing member.

A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.