A semiconductor package includes: a lower package; and an upper package stacked on the lower package, wherein the lower package includes: a first redistribution structure; a semiconductor chip mounted on the first redistribution structure; a first molding layer surrounding the semiconductor chip on the first redistribution structure; and first vertical connection conductors disposed on the first redistribution structure and vertically passing through the first molding layer, wherein the upper package includes: a second molding layer disposed on the lower package; second vertical connection conductors vertically passing through the second molding layer and electrically connected to the first vertical connection conductors; and an antenna structure disposed on the second molding layer.

Methods, systems, and apparatus for cleaning and drying a tape-frame substrate are provided. In embodiments, an apparatus for supporting a tape-frame substrate includes a chuck having a first side and a second side opposite the first side, the first side having a convex surface configured to support the tape-frame substrate; and a plurality of channels extending through the chuck and having outlets along the first side, wherein the plurality of channels are configured to dispense fluid from the outlets along the convex surface of the first side. In embodiments, a support system includes the chuck and a holder configured to mount a tape-frame substrate to the chuck. The plurality of channels are configured to dispense fluid from the outlets and between the tape-frame substrate and the convex surface of the chuck when the tape-frame substrate is mounted to the chuck.

A semiconductor device package includes a substrate, a partition structure and a polymer film. The partition structure is disposed on the substrate and defines a space for accommodating a semiconductor device. The polymer film is adjacent to a side of the partition structure distal to the substrate. A first side surface of the polymer film substantially aligns with a first side surface of the partition structure.

A method for taping a wafer is disclosed. A wafer taping device comprising a wafer stage is provided. A wafer is mounted and secured on the wafer stage. A tape is delivered along a first direction over the wafer. The tape is forced into adhesion with a surface of the wafer in a non-contact manner. The tape is cut along a perimeter of the wafer.

Implementations of methods of making a semiconductor device may include: providing a partial semiconductor wafer. The method may also include providing a wafer holder including a tape portion with one or more openings through the tape portion. The method may include mounting the partial semiconductor wafer over the one or more openings in the tape portion of the wafer holder and providing an electrical connection to the partial semiconductor wafer through the one or more openings in the tape portion during probe test.

A semiconductor stack and a method for manufacturing the same are disclosed. The semiconductor stack includes a lower chip, an upper chip disposed over the lower chip, an upper lateral-side passivation layer surrounding side surfaces of the upper chip, and a plurality of bonding pads and a bonding passivation layer disposed between the upper chip and the lower chip.

A method of manufacturing a semiconductor device includes performing one or more grinding processes on a backside surface of a device wafer to thin the device wafer from a first thickness to a second thickness. A first chemical mechanical polish (CMP) process is performed on the backside surface of the device wafer to thin the device wafer from the second thickness to a third thickness. A second CMP process is performed on the backside surface of the device wafer to selectively remove device wafer material that is disposed over an active device area of the semiconductor device, where a removal rate of the device wafer material is a function of depth.

A method of manufacturing chips includes a preparing step of preparing a wafer unit in which a wafer having a plurality of devices formed thereon is affixed to a tape with a die-attach layer being interposed therebetween, the die-attach layer including fillers, and the devices are protected by a protective member and a face side of the wafer is exposed along the projected dicing lines, a wafer processing step of performing plasma etching on the wafer from the face side thereof to divide the wafer and expose the die-attach layer along the projected dicing lines, a die-attach layer processing step of performing plasma etching on the die-attach layer from the face side of the wafer, and a cleaning step of ejecting a fluid to the face side of the wafer to remove filler residuals along the projected dicing lines from the wafer unit.

A semiconductor device may include an embedded device comprising through silicon vias (TSVs) extending from a first surface to a second surface opposite the first surface, wherein the embedded device comprises an active device, a semiconductor die comprising an active surface formed at the first surface, an integrated passive device (IPD), or a passive device. Encapsulant may be disposed over at least five sides of the embedded device. A first electrical interconnect structure may be coupled to a first end of the TSV at the first surface of the embedded device, and a second electrical interconnect structure may be coupled to a second end of the TSV at the second surface of the embedded device. A semiconductor die (e.g. a system on chip (SoC), memory device, microprocessor, graphics processor, or analog device), may be mounted over the first electrical interconnect of the TSV.

A method of making a semiconductor device may include providing a large semiconductor die comprising conductive interconnects with a first encapsulant disposed over four side surfaces of the large semiconductor die, over the active surface of the large semiconductor die, and around the conductive interconnects. A first build-up interconnect structure may be formed over the large semiconductor die and over the first encapsulant. Vertical conductive interconnects may be formed over the first build-up interconnect structure and around an embedded device mount site. An embedded device comprising through silicon vias (TSVs) may be disposed over the embedded device mount site. A second encapsulant may be disposed over the build-up structure, and around at least five sides of the embedded device. A second build-up structure may be formed disposed over the planar surface and configured to be electrically coupled to the TSVs of the embedded device and the vertical conductive interconnects.