A method for manufacturing an integrated circuit (IC) structure is provided. The method includes: etching a first recess and a second recess in a substrate; forming a sacrificial epitaxial plug in the first recess in the substrate; forming a first epitaxial feature and a second epitaxial feature respectively in the first recess and the second recess, wherein the first epitaxial feature is over the sacrificial epitaxial plug; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure over the first epitaxial feature and the second epitaxial feature respectively; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing the sacrificial epitaxial plug and the first epitaxial feature to form a backside via opening exposing a backside of the first source/drain epitaxial structure; and forming a backside via in the backside via opening.

A back grinding tape including a hard coating layer, an intermediate layer including a polyurethane-based resin, and an adhesive layer provided has an excellent water resistance, thus easily protecting patterns, and has an excellent adhesion between each layer, and thus each layer is not separated in the process of removing the tape, such that the back grinding tape is suitable for a back grinding process.

A thermosetting adhesive sheet capable of reducing semiconductor wafer warping and chipping and a method for manufacturing a semiconductor device includes a thermosetting adhesive layer formed from a resin composition containing a resin component and a filler, the resin component containing an epoxy compound and a curing agent, a total value obtained by multiplying the reciprocal of epoxy equivalent of the epoxy compound by content of the epoxy compound in the resin component being 1.15E−04 or more, and blending amount of the filler being 50 pts. mass or more with respect to 100 pts. mass of the resin component; the thermosetting adhesive sheet is applied to a ground surface of a semiconductor and cured before dicing.

The invention relates to methods of processing a wafer, having on one side a device area with a plurality of devices. In particular, the invention relates to a method which comprises providing a protective film, and applying the protective film to the side of the wafer being opposite to the one side, so that at least a central area of a front surface of the protective film is in direct contact with the side of the wafer being opposite to the one side. The method further comprises applying an external stimulus to the protective film during and/or after applying the protective film to the side of the wafer being opposite to the one side, so that the protective film is attached to the side of the wafer being opposite to the one side, and processing the one side of the wafer and/or the side of the wafer being opposite to the one side.

An electronic component includes a mold layer and a semiconductor die including a low ohmic first portion and a high ohmic second portion. The low ohmic first portion has an active area. The high ohmic second portion is arranged on the mold layer.

Semiconductor dies with edges protected and methods for generating the semiconductor dies are disclosed. Further, the disclosed methods provide for separating the semiconductor dies without using a dicing technique. In one embodiment, trenches are formed on a front side of a substrate including semiconductor dies. Individual trenches correspond to scribe lines of the substrate where each trench has a depth greater than a final thickness of the semiconductor dies. A composite layer may be formed on sidewalls of the trenches to protect the edges of the semiconductor dies. The composite layer includes a metallic layer that shields the semiconductor dies from electromagnetic interference. Subsequently, the substrate may be thinned from a back side to singulate individual semiconductor dies from the substrate.

A laminated device chip manufacturing method includes: a first wafer processing step of exposing a first resin layer disposed in first grooves to an undersurface side of a first wafer by thinning the first wafer fixed to a first support; a laminating step of laminating the undersurface side of the first wafer and a top surface side of a second wafer to each other such that the first resin layer exposed to the undersurface side of the first wafer and a second resin layer disposed in second grooves of the second wafer coincide with each other; a second wafer processing step of exposing the second resin layer disposed in the second grooves to an undersurface side of the second wafer by thinning the second wafer; and a resin layer cutting step of manufacturing laminated device chips by cutting the first resin layer and the second resin layer.

A method for manufacturing a semiconductor element includes: providing a wafer comprising first and second regions at an upper surface of the wafer, the second region being located at a periphery of the first region and being at a lower position than the first region; and forming a semiconductor layer made of a nitride semiconductor at the upper surface of the wafer. In a top-view, the first region comprises an extension portion at an end portion of the first region in a first direction that passes through the center of the wafer parallel to an m-axis of the semiconductor layer, the extension portion extending in a direction from a center of the wafer toward an edge of the wafer or in a direction from an edge of the wafer toward a center of the wafer.

A semiconductor device includes a support, a semiconductor chip, a first insulating film, and a wiring layer. The support comprises a first electrode. The semiconductor chip has a first surface facing the support and a second surface facing away from the support with a second electrode thereon. The first insulating film has a first portion in contact with the first surface and a second portion in contact with at least one side surface of the semiconductor chip. The wiring layer connects the first electrode to the second electrode. The wiring layer is on the support, the second surface of the semiconductor chip, a side surface of the second portion of the first insulating film.

Provided is a pressure-sensitive adhesive composition to be used in a pressure-sensitive adhesive tape for semiconductor processing, which has an excellent unevenness-embedding property and an excellent pressure-sensitive adhesive property, and can prevent adhesive residue on an adherend at the time of its peeling. The pressure-sensitive adhesive composition to be used in a pressure-sensitive adhesive tape for semiconductor processing includes a base polymer and a photopolymerization initiator, wherein the base polymer is a polymer obtained by polymerizing a monomer composition containing a polymer having a hydroxy group and a monomer represented by the following formula:

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where “n” represents an integer of 1 or more.