A method and apparatus for bonding a processor wafer with a microchannel wafer/glass manifold to form a bonded wafer structure are provided. A glass fixture is also provided for protecting C4 solder bumps on chips disposed on the processor wafer. When the glass fixture is positioned on the processor wafer, posts extending from the glass fixture contact corresponding regions on the processor wafer devoid of C4 solder bumps, so that the glass fixture protects the C4 solder bumps during wafer bonding. The method involves positioning the processor wafer/glass fixture and the microchannel wafer/glass manifold in a metal fixture having one or more alignment structures adapted to engage corresponding alignment elements formed in the processor wafer, glass fixture and/or glass manifold. The metal fixture secures the wafer components in place and, after melting solder pellets disposed between the processor wafer/glass fixture and microchannel wafer/glass manifold, a bonded wafer structure is formed.

A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.

Semiconductor devices having recessed edges with plated structures, semiconductor assemblies formed therefrom, and associated systems and methods are disclosed herein. In one embodiment, a semiconductor assembly includes a first semiconductor device and a second semiconductor device. The first semiconductor device can include an upper surface and a first dielectric layer over the upper surface, the second semiconductor device can include a lower surface and a second dielectric layer over the lower surface, and the first and second dielectric layers can be bonded to couple the first and second semiconductor devices. The first and second dielectric layers can each include a plurality of inwardly extending recesses exposing a plurality of metal structures on the respective upper and lower surfaces, and the upper surface recesses and metal structures can correspond to the lower surface recesses and metal structures. The metal structures can be electrically coupled by plated structures positioned in the recesses.

It is an object of the present disclosure to provide a method of manufacturing a thin semiconductor element having a low defect rate. A method of manufacturing a semiconductor element according to the present disclosure includes: forming a metal thin film on an electrode protection layer of a circuit element substrate and a support substrate in vacuum; attaching the metal thin film of the circuit element substrate and the metal thin film of the support substrate by an atomic diffusion joining method; removing a semiconductor substrate by polishing to expose a circuit element; joining a transfer substrate to an exposed surface of the circuit element; and detaching the support substrate from the circuit element after joining the transfer substrate.

A method of partitioning a wafer includes defining a scribe line surrounding a set of dies. The method further includes etching a plurality of trenches into the wafer, wherein each trench of the plurality of trenches is located between adjacent dies of the set of dies, and a width of each trench of the plurality of trenches is less than a width of the scribe line. The method further includes thinning the wafer to expose a bottom surface of the plurality of trenches. The method further includes cutting along the scribe line to separate the set of dies from another portion of the wafer.

To provide a manufacturing method of a semiconductor device including a semiconductor substrate, the manufacturing method of the semiconductor device including a sticking for sticking a protection tape to a first surface of the semiconductor substrate, a first grinding for supporting the protection tape and grinding a second surface of the semiconductor substrate that is a surface on the opposite side of the first surface, a protection tape cutting for supporting the second surface of the semiconductor substrate and flattening the protection tape, and a second grinding for supporting the protection tape and grinding the second surface of the semiconductor substrate. In the second grinding, in order to leave a convex part in an outer circumference of the semiconductor substrate, an inside of the convex part may be ground.

A three dimensional multi-die package includes a first die and second die. The first die includes a contact attached to solder. The second die is thinned by adhesively attaching a handler to a top side of the second die and thinning a bottom side of the second die. The second die includes a multilayer contact of layered metallurgy that inhibits transfer of adhesive thereto. The layered metallurgy includes at least one layer that is wettable to the solder. The multilayer contact may include a Nickel layer, a Copper layer upon the Nickel layer, and a Nickel-Iron layer upon the Copper layer. The multilayer contact may also include a Nickel layer, a Copper-Tin layer upon the Nickel layer, and a Tin layer upon the Copper-Tin layer.

An adhesive bonding method that includes bonding a handling wafer to a front side surface of a device wafer with an adhesive comprising N-substituted maleimide copolymers. The device wafer may then be thinned from the backside surface of the device wafer while the device wafer is adhesively engaged to the handling wafer. The adhesive can then be removed by laser debonding, wherein the device wafer is separated from the handling wafer.

A method for manufacturing an integrated circuit (IC) structure is provided. The method includes: etching a first recess and a second recess in a substrate; forming a sacrificial epitaxial plug in the first recess in the substrate; forming a first epitaxial feature and a second epitaxial feature respectively in the first recess and the second recess, wherein the first epitaxial feature is over the sacrificial epitaxial plug; forming a first source/drain epitaxial structure and a second source/drain epitaxial structure over the first epitaxial feature and the second epitaxial feature respectively; forming a gate structure laterally between the first source/drain epitaxial structure and the second source/drain epitaxial structure; removing the sacrificial epitaxial plug and the first epitaxial feature to form a backside via opening exposing a backside of the first source/drain epitaxial structure; and forming a backside via in the backside via opening.

Some implementations provide a device that includes a passive component and a substrate coupled to the passive component, where a surface of the substrate comprises a first irradiated portion. In some implementations, the first irradiated portion is located in an offset portion of the substrate. Some implementations provide an integrated device that includes a device layer and a substrate coupled to the device layer, where a surface of the substrate comprises a first irradiated portion. In some implementations, the first irradiated portion is located in an offset portion of the substrate.