Patent classifications
H01L2221/6834
Methods of fabricating semiconductor devices
A method of fabricating a semiconductor device is provided. The method may include preparing a substrate having a first surface and a second surface, forming a via hole exposing at least a portion of the substrate from the first surface of the substrate, forming a first insulating film on an inner wall of the via hole, forming a conductive connection part filling an inside of the via hole including the first insulating film, polishing the second surface of the substrate until the conductive connection part is exposed, and selectively forming a second insulating film on the second surface of the substrate using an electrografting method to expose the conductive connection part.
Semiconductor device and method of forming conductive pillar having an expanded base
A semiconductor device has a first semiconductor die and conductive vias in the first semiconductor die. The conductive vias can be formed by extending the vias partially through a first surface of the first semiconductor die. A portion of a second surface of the first semiconductor die is removed to expose the conductive vias. A plurality of conductive pillars is formed over the first surface the first semiconductor die. The conductive pillars include an expanded base electrically connected to the conductive vias. A width of the expanded base of the conductive pillars is greater than a width of a body of the conductive pillars. A conductive layer is formed over a second surface of the first semiconductor die. The conductive layer is electrically connected to the conductive vias. A second semiconductor die is mounted to the first semiconductor die with a second conductive pillar having an expanded base.
Stiffener tape for electronic assembly
Some example forms relate to a stiffener tape for a wafer. The stiffener tape includes a mounting tape and a stiffener removably attached to the mounting tape. The stiffener tape further includes a die attach film attached to the stiffener. Other example forms relate to an electronic assembly that includes a wafer and a stiffener tape attached to the wafer. The stiffener tape includes a die attach film mounted to the wafer. A stiffener is attached to the die attach film and a mounting tape is removably attached to the stiffener. Still other example forms relate to a method that includes forming a stiffener tape which includes a mounting tape, a stiffener removably attached to the mounting tape and a die attach film attached to the stiffener.
Display with embedded pixel driver chips
Embodiments describe a display integration scheme in which an array of pixel driver chips embedded front side up in an insulator layer. A front side redistribution layer (RDL) spans across and is in electrical connection with the front sides of the array of pixel driver chips, and an array of light emitting diodes (LEDs) is bonded to the front side RDL. The pixel driver chips may be located directly beneath the display area of the display panel.
Semiconductor wafer and method of backside probe testing through opening in film frame
A semiconductor test system has a film frame including a tape portion with one or more openings through the tape portion. The opening is disposed in a center region of the tape portion of the film frame. The film frame may have conductive traces formed on or through the tape portion. A thin semiconductor wafer includes a conductive layer formed over a surface of the semiconductor wafer. The semiconductor wafer is mounted over the opening in the tape portion of the film frame. A wafer probe chuck includes a lower surface and raised surface. The film frame is mounted to the wafer probe chuck with the raised surface extending through the opening in the tape portion to contact the conductive layer of the semiconductor wafer. The semiconductor wafer is probe tested through the opening in the tape portion of the film frame.
Semiconductor wafer and method of probe testing
Implementations of methods of making a semiconductor device may include: providing a partial semiconductor wafer. The method may also include providing a wafer holder including a tape portion with one or more openings through the tape portion. The method may include mounting the partial semiconductor wafer over the one or more openings in the tape portion of the wafer holder and providing an electrical connection to the partial semiconductor wafer through the one or more openings in the tape portion during probe test.
Semiconductor package
A semiconductor package is provided. The semiconductor package comprising a first redistribution structure comprising a first redistribution pattern; a first semiconductor chip on the first redistribution structure, the first semiconductor chip comprising a semiconductor substrate comprising a first surface and a second surface, a first back end of line (BEOL) structure on the first surface of the semiconductor substrate and comprising a first interconnect pattern, and a second BEOL structure on the second surface of the semiconductor substrate and comprising a second interconnect pattern; a molding layer covering a sidewall of the first semiconductor chip; a second redistribution structure on the first semiconductor chip and the molding layer and comprising a second redistribution pattern electrically connected to the second interconnect pattern.
3D semiconductor device and structure with oxide bonds
A semiconductor device, the device including: a plurality of transistors, where at least one of the plurality of transistors includes a first single crystal channel, where at least one of the plurality of transistors includes a second single crystal channel, where the second single crystal channel is disposed above the first single crystal channel, where at least one of the plurality of transistors includes a third single crystal channel, where the third single crystal channel is disposed above the second single crystal channel, where at least one of the plurality of transistors includes a fourth single crystal channel, and where the fourth single crystal channel is disposed above the third single crystal channel; and at least one region of oxide to oxide bonds.
EMI shield for high frequency layer transferred devices
Various methods and devices that involve EMI shields for radio frequency layer transferred devices are disclosed. One method comprises forming a radio frequency field effect transistor in an active layer of a semiconductor on insulator wafer. The semiconductor on insulator wafer has a buried insulator side and an active layer side. The method further comprises bonding a second wafer to the active layer side of the semiconductor on insulator wafer. The method further comprises forming a shield layer for the semiconductor device. The shield layer comprises an electrically conductive material. The method further comprises coupling the radio frequency field effect transistor to a circuit comprising a radio frequency component. The method further comprises singulating the radio frequency field effect transistor, radio frequency component, and the shield layer into a die. The shield layer is located between a substrate of the radio frequency component and the radio frequency field effect transistor.
Wafer processing method
A wafer processing method for dividing a wafer into individual device chips along division lines is disclosed. The wafer processing method includes a back grinding step of grinding the back side of the wafer in the condition where a protective tape is attached to the front side of the wafer, thereby reducing the thickness of the wafer to a predetermined thickness, and a reinforcing insulation seal mounting step of mounting a reinforcing insulation seal capable of transmitting infrared light on the back side of the wafer. The wafer processing method further includes a modified layer forming step of applying a laser beam along each division line to thereby form a modified layer inside the wafer along each division line and a wafer dividing step of applying an external force to the wafer to thereby divide the wafer into the individual device chips along each division line.