H01L2221/6835

Vertically stacked transistors in a fin

An apparatus is provided which comprises: a fin; a layer formed on the fin, the layer dividing the fin in a first section and a second section; a first device formed on the first section of the fin; and a second device formed on the second section of the fin.

DE-BONDING OF THICK FILMS FROM CARRIER AND METHODS THEREOF

A method for coating a multi-layered polymer film is disclosed including coating a first layer of polyimide onto a carrier, curing the first layer of polyimide by subjecting the first layer of polyimide to an elevated temperature, depositing a first layer of metal onto the cured first layer of polyimide, coating a second layer of polyimide onto the first layer of metal, and curing the second layer of polyimide by subjecting the second layer of polyimide to an elevated temperature. A flexible electronic device is also disclosed, including multiple interposed layers of polyimide and layers of metal, a dielectric barrier layer disposed on the top layer of polyimide, and a thin film transistor-based device disposed on the dielectric barrier layer. The flexible electronic device has little to no curl.

3D SEMICONDUCTOR DEVICE AND STRUCTURE WITH REDUNDANCY

A 3D semiconductor device with a built-in-test-circuit (BIST), the device comprising: a first single-crystal substrate with a plurality of logic circuits disposed therein, wherein said first single-crystal substrate comprises a device area, wherein said plurality of logic circuits comprise at least a first interconnected array of processor logic, wherein said plurality of logic circuits comprise at least a second interconnected set of circuits comprising a first logic circuit, a second logic circuit, and a third logic circuit, wherein said second interconnected set of logic circuits further comprise switching circuits that support replacing said first logic circuit and/or said second logic circuit with said third logic circuit; and said built-in-test-circuit (BIST), wherein said first logic circuit is testable by said built-in-test-circuit (BIST), and wherein said second logic circuit is testable by said built-in-test-circuit (BIST).

CHUCK, LAMINATION PROCESS, AND MANUFACTURING METHOD OF SEMICONDUCTOR PACKAGE USING THE SAME

A lamination chuck for lamination of film materials includes a support layer and a top layer. The top layer is disposed on the support layer. The top layer includes a polymeric material having a Shore A hardness lower than a Shore hardness of a material of the support layer. The top layer and the support layer have at least one vacuum channel formed therethrough, vertically extending from a top surface of the top layer to a bottom surface of the support layer.

RECONSTITUTED WAFER-TO-WAFER HYBRID BONDING INTERCONNECT ARCHITECTURE WITH KNOWN GOOD DIES

Embodiments disclosed herein include die modules and methods of making die modules. In an embodiment, a die module comprises a first die with a set of first pads with surfaces that are substantially coplanar with a surface of a first dielectric layer. In an embodiment, the die module further comprises a second die with a set of second pads with surfaces that are substantially coplanar with a surface of a second dielectric layer. In an embodiment the first pads are bonded to the second pads and the first dielectric layer is bonded to the second dielectric layer.

3D SEMICONDUCTOR DEVICE AND STRUCTURE
20230207398 · 2023-06-29 · ·

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level, where the via has a diameter of less than 450 nm, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the third metal layer by at least 50%.

Separation apparatus

A yield in a separation process is improved. A separation apparatus which enables easy separation in a large-area substrate is provided. The separation apparatus has a function of dividing a process member into a first member and a second member and includes a support body supply unit, a support body hold unit, a transfer mechanism, a direction changing mechanism, and a structure body. The structure body bonds a support body to a surface of the first member. When at least part of the process member is located between the direction changing mechanism and the structure body or the pressure applying mechanism, the shortest distance between the direction changing mechanism and a first plane including the surface of the first member is longer than the shortest distance between the first plane and the structure body or the pressure applying mechanism.

Wrap-around contact structures for semiconductor fins
11688637 · 2023-06-27 · ·

Wrap-around contact structures for semiconductor fins, and methods of fabricating wrap-around contact structures for semiconductor fins, are described. In an example, an integrated circuit structure includes a semiconductor fin having a first portion protruding through a trench isolation region. A gate structure is over a top and along sidewalls of the first portion of the semiconductor fin. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor fin. The epitaxial structure has substantially vertical sidewalls in alignment with the second portion of the semiconductor fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor fin and along the substantially vertical sidewalls of the epitaxial structure.

Semiconductor device with two-dimensional materials

The present disclosure describes a method that includes forming a first two-dimensional (2D) layer on a first substrate and attaching a second 2D layer to a carrier film. The method also includes bonding the second 2D layer to the first 2D layer to form a heterostack including the first and second 2D layers. The method further includes separating the first 2D layer of the heterostack from the first substrate and attaching the heterostack to a second substrate. The method further includes removing the carrier film from the second 2D layer.

Debonding a glass substrate from carrier using ultrasonic wave

A process for making a device comprising a thin functional substrate comprising bonding the functional substrate to a carrier substrate, forming functional components on the functional subsrate, and debonding the functional substrate from the carrier substrate by applying ultrasonic wave to the bonding interface. The application of ultrasonic wave aids the debonding step by reducing the tensile stress the functional substrate may experience.