According to one embodiment, a wafer for electronic components, includes a sapphire substrate including a first surface and a second surface on an opposite side to the first surface and a plurality of electronic components located on a side of the first surface, and the sapphire substrate includes trench portions located between respective adjacent electronic components, and the trench portions extend linearly in plan view.

A micro-LED manufacturing device includes: a wafer stage on which a wafer is positioned; a substrate stage on which a substrate is positioned; a lower base formed below the substrate stage; a first driving member formed on the substrate stage so as to move the wafer stage; and a second driving member formed on the lower base so as to move the substrate stage. The micro-LED manufacturing device is formed such that the wafer stage moves over the substrate stage, and thus the substrate stage and the wafer stage can move synchronously with respect to the lower base.

A method for mass transfer, a light-emitting diode (LED) display device, and a display apparatus are provided. The method includes: applying an insulating-adhesive on a growth substrate, where the insulating-adhesive applied is between two adjacent LED chips; placing the growth substrate above a display backplane, where a distance between the growth substrate and the display backplane after placing is greater than a height of an LED chip; forming an insulating-adhesive column between the growth substrate and the display backplane by softening the insulating-adhesive through heating, where the softened insulating-adhesive subjected to heating is adhered to the display backplane; separating the LED chip from the growth substrate, to make the separated LED chip fall onto a corresponding pad-group through a channel formed by insulating-adhesive columns around the separated LED chip; and bonding the fallen LED chip with the corresponding pad-group on the display backplane.

A wafer is positioned in an opening of a first frame. The wafer is pressure-bonded at one surface thereof to a first tape together with the first frame, onto a second tape pressure-bonded to a second frame. The wafer is processed by pressure-bonding the second tape, which is pressure-bonded to the second frame having an outer diameter smaller than an inner diameter of the opening of the first frame, to another surface of the wafer, cutting the first tape along an outer periphery of the second frame, imparting an external stimulus to the first tape to lower a pressure-bonding force with which the first tape is pressure-bonded to the one surface of the wafer, and peeling off the first tape from the one surface of the wafer pressure-bonded to the second tape.

Provided is a micro semiconductor chip transfer substrate including a base substrate, guide rails provided on the base substrate extending in a direction parallel to each other and spaced apart from each other, and a plurality of grooves provided in the base substrate between the guide rails and configured to accommodate micro semiconductor chips.

The present invention relates to an ultra-thin light-emitting diode (LED) electrode assembly, a manufacturing method of the ultra-thin LED electrode assembly, and a transfer film of an ultra-thin LED used for manufacturing the ultra-thin LED electrode assembly and relates to an ultra-thin LED electrode assembly in which a plurality of LED elements are simultaneously transferred using a laser-assisted multi-chip transfer printing method to form and pattern the LED elements, thereby preventing process defects caused by omission of the LED elements during transfer and deviation thereof from an electrode line, and defects such as dark spots caused in an LED display, a manufacturing method of the ultra-thin LED electrode assembly, and a transfer film of an ultra-thin LED used for manufacturing the ultra-thin LED electrode assembly.

The present invention discloses a substrate configured to receive a plurality of micro elements on a carrier board. The substrate comprises a body, a first conductive bump, and a second conductive bump. The body has a first surface, a transfer area is defined within the first surface, and a central portion and a peripheral portion is defined within the transfer area. The first conductive bump, disposed on the central portion, has a first volume. The second conductive bump, disposed on the peripheral portion, has a second volume. Wherein the first volume is different from the second volume.

Various embodiments of the present technology provide for the ultra-high density heterogenous integration, enabled by nano-precise pick-and-place assembly. For example, some embodiments provide for the integration of modular assembly techniques with the use of prefabricated blocks (PFBs). These PFBs can be created on one or more sources wafers. Then using pick-and-place technologies, the PFBs can be selectively arranged on a destination wafer thereby allowing Nanoscale-aligned 3D Stacked Integrated Circuit (N3-SI) and the Microscale Modular Assembled ASIC (M2A2) to be efficiently created. Some embodiments include systems and techniques for the construction of construct semiconductor devices which are arbitrarily larger than the standard photolithography field size of 26×33 mm, using pick-and-place assembly.

The present disclosure relates to a semiconductor substrate manufacturing method including: forming a catalytic metal film composed of a transition metal on a main surface to be polished of a workpiece substrate composed of any one of diamond, silicon carbide, gallium nitride, and sapphire; and providing relative movement between the workpiece substrate on which the catalytic metal film has been formed and a polishing platen in an oxidant solution to remove a compound generated by chemical reaction of an active radical generated by reaction of the catalytic metal film and the oxidant solution and a surface atom on the main surface of the workpiece substrate to thereby polish the workpiece substrate. The manufacturing method further includes: bonding the polished workpiece substrate to a nitride semiconductor layer by room temperature bonding; and removing a support substrate and a resin adhesive layer.

A semiconductor element arrangement structure is provided. The semiconductor element arrangement structure includes a carrier substrate, first and second adhesive layers respectively disposed on the carrier substrate and separated from each other, and first and second semiconductor elements disposed on the first and second adhesive layers, respectively. The first semiconductor element has first and second electrodes on the same side of the first semiconductor element, and the second semiconductor element has third and fourth electrodes on the same side of the second semiconductor element. The first adhesive layer is in direct contact with the first and second electrodes, and the second adhesive layer is in direct contact with the third and fourth electrodes. The first adhesive layer has a first width between the first and second electrodes and has a second width not between the first and second electrodes that is less than the first width.