The present disclosure relates to a method of making an electronic device comprising a first wafer including at least one trench and a second wafer, the second wafer being bonded, by hybrid bonding, to the first wafer, so as to form, at the level of the trench, at least one enclosed space, empty or gas-filled.

According to a preferred embodiment of the method of the invention, an assembly is produced comprising a temporary wafer and one or more tiles that are removably attached to the temporary wafer, preferably through a temporary adhesive layer. The tiles comprise a carrier portion and an active material portion. The active material portion is attached to the temporary carrier. The assembly further comprises a single continuous layer of the first material surrounding each of the one or more tiles. Then the back side of the carrier portions of the tiles and of the continuous layer of the first material are simultaneously planarized, and the planarized back sides of the tiles and of the continuous layer of the first material are bonded to a permanent carrier wafer, after which the temporary carrier wafer is removed. The method results in a hybrid wafer comprising a planar top layer formed of the material of the continuous layer with one or more islands embedded therein, the top layer of the islands being formed by the top layer of the active material portion of the one or more tiles.

A method for making a micro LED display panel not requiring high-accuracy or individual positioning includes providing a carrier substrate with micro LEDs, providing a TFT substrate including a driving circuit, and forming a conductive connecting element, an insulating layer, and a contact electrode layer on the TFT substrate. The insulating layer and the contact electrode layer are patterned to define a through hole, the first electrode is placed against the contact electrode layer, and different voltages Vref and Vdd are applied to the contact electrode layer and to the conductive connecting element respectively, creating an electrostatic attraction. The micro LEDs and the first electrode are transferred from the carrier substrate onto the TFT substrate; and the conductive connecting element is bonded to the first electrode. The method of making is simple. A micro LED display panel made by the method is also provided.

A method of manufacturing an electronic device, comprising: providing a carrier substrate with a plurality of light-emitting units disposed thereon, the plurality of light-emitting units being spaced with a first pitch (P1) in a first direction and a second pitch (P2) in a second direction that is perpendicular to the first direction; providing a driving substrate; and transferring at least a portion of the plurality of light-emitting units to the driving substrate to form a transferred portion of the plurality of light-emitting units on the driving substrate, the transferred portion being spaced with a third pitch (P3) in a third direction and a fourth pitch (P4) in a fourth direction that is perpendicular to the third direction; wherein the first pitch (P1), the second pitch (P2), the third pitch (P3), and the fourth pitch (P4) are satisfied following relations: P3=mP1; and P4=nP2, m and n are positive integers.

This invention relates to the process of correcting misalignment and filling voids after a microdevice transfer process. The process involves transfer heads, measurement of offset and misalignment in horizontal, vertical, and rotational errors. An execution of the new offset vector for the next transfer corrects the alignment.

A method of manufacturing a semiconductor element includes: forming a first semiconductor layer (SL1) and a second semiconductor layer (SL2) larger in thickness than the first semiconductor layer (SL1) on a mask layer (ML) including a first opening portion (K1) and a second opening portion (K2); forming a first device layer (DL1) and a second device layer (DL2); and bonding the first device layer (DL1) and the second device layer (DL2) to a support substrate (SK).

A device transfer substrate includes a plurality of recesses, wherein each of the plurality of recesses includes a first region having a shape of a first figure, a second region having a shape of a second figure, and an overlapping region formed as a portion of the first region partially overlaps a portion of the second region, wherein a maximum width of the overlapping region in a direction intersecting with a straight line passing through a center of the first figure and a center of the second figure is less than a diameter or a diagonal length of the first figure and less than a diameter or a diagonal length of the second figure.

A multi-chip assembly includes: a first power transistor die having a source terminal facing a first direction and a drain terminal facing a second direction opposite the first direction; and a second power transistor die having a drain terminal facing the first direction, and a source terminal facing the second direction. A dielectric material occupies a gap between the first power transistor die and the second power transistor die, and secures the first power transistor die and the second power transistor die to one another. A metallization connects the source terminal of the first power transistor die to the drain terminal of the second power transistor die at a same side of the multi-chip assembly. The gap occupied by the dielectric material is less than 70 μm. Corresponding methods of producing multi-chip assemblies are also described.

A multi-component transistor structure includes components each comprising an individual, discrete, and separate component substrate and a component transistor. The component transistor includes a transistor element having a transistor element resistance. A component connection is disposed external to the transistor element and has a connection resistance. The component connection electrically connects the transistor elements in the components in parallel. The connection resistance is less than the transistor element resistance of at least one corresponding transistor element, less than an average of the transistor element resistances of all of the corresponding transistor elements, or less than the sum of all of the transistor element resistances of all of the corresponding transistor elements. The component transistors are functionally similar and at least one of the components is disposed on another different one of the components in a component stack.

A semiconductor chip includes a chip body, a redistribution layer pattern disposed on a surface of the chip body, an alignment mark pattern disposed to be spaced apart from the redistribution layer pattern on the surface of the chip body, a first insulating pattern disposed to contact a side surface of the redistribution layer pattern and a side surface of the alignment mark pattern on the surface of the chip body, a second insulating pattern disposed on the redistribution layer pattern to protect the redistribution layer pattern, and an alignment mark protection pattern disposed on the alignment mark pattern.