A thermosetting sheet according to the present invention includes a thermosetting resin and a thermoplastic resin, in which a thickness change rate when a temperature is changed from 25° C. to 200° C. is 0% or more and 10% or less.

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level, where the via has a diameter of less than 450 nm, where the via includes tungsten, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.

According to one embodiment, a method for manufacturing a semiconductor device includes placing a semiconductor chip on a first surface of a support substrate, forming a first resin layer covering the semiconductor chip on the first surface, and forming a second resin layer on a second surface of the support substrate. The second surface is opposite the first surface. In some examples, the second resin layer can be formed to counteract or mitigate warpage of the support substrate that might otherwise result from use of the first resin layer.

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer and a plurality of first transistors; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level, where the via has a diameter of less than 450 nm, where the via includes tungsten, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.

Embodiments of this application provide a semiconductor structure, an electronic device, and a manufacture method for a semiconductor structure, and relate to the field of heat dissipation technologies for electronic products. An example semiconductor structure includes a semiconductor device, a bonding layer, a substrate, a conducting via, and a metal layer. The semiconductor device is disposed on an upper surface of the substrate by using the bonding layer. The metal layer is disposed on a lower surface of the substrate. The substrate includes a base plate, a groove formed on the base plate, and a diamond accommodated in the groove. The conducting via penetrates the substrate, the bonding layer, and at least a part of the semiconductor device, and is electrically connected to the metal layer. The groove bypasses the conducting via.

In a described example, a method of forming a semiconductor apparatus includes applying a layer of an electrically insulating material on a backside of a semiconductor wafer having a plurality of integrated circuit dice. The method also includes mounting the wafer to dicing tape with a die attach film, in which the die attach film is between the backside layer and the dicing tape, and cutting the wafer into respective dice.

Packaging method for forming the panel-level chip device is provided. The panel-level chip device includes a plurality of first bare chips disposed on a supporting base, and a plurality of first connection pillars. The panel-level chip device also includes a first encapsulation layer, and a first redistribution layer. The first redistribution layer includes a plurality of first redistribution elements and a plurality of second redistribution elements. Further, the panel-level chip device includes a solder ball group including a plurality of first solder balls. First connection pillars having a same electrical signal are electrically connected to each other by a first redistribution element. Each of remaining first connection pillars is electrically connected to one second redistribution element. The one second redistribution element is further electrically connected to a first solder ball of the plurality of first solder balls.

A semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure.

A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer; a first metal layer disposed over the first single crystal silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; and a via disposed through the second level, where the via has a diameter of less than 450 nm, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the third metal layer by at least 50%.

An underfill film material and a method for manufacturing a semiconductor device using the same which enables voidless mounting and favorable solder bonding properties are provided. An underfill material is used which contains an epoxy resin, an acid anhydride, an acrylic resin and an organic peroxide, the underfill material exhibits non-Bingham fluidity at a temperature ranging from 60° C. to 100° C., a storage modulus G′ measured by dynamic viscosity measurement has an inflection point in an angular frequency region below 10E+02 rad/s, and the storage modulus G′ in the angular frequency below the inflection point is 10E+05 Pa or more and 10E+06 Pa or less. This enables voidless packaging and excellent solder connection properties.