Embodiments of the present invention provide for the application of strain inducing layers to enhance the mobility of transistors formed on semiconductor-on-insulator (SOI) structures. In one embodiment, a method for fabricating an integrated circuit is disclosed. In a first step, active circuitry is formed in an active layer of a SOI wafer. In a second step, substrate material is removed from a substrate layer disposed on a back side of the SOI wafer. In a third step, insulator material is removed from the back side of the SOI wafer to form an excavated insulator region. In a fourth step, a strain inducing material is deposited on the excavated insulator region. The strain inducing material interacts with the pattern of excavated insulator such that a single layer provides both tensile and compressive stress to p-channel and n-channel transistors, respectively. In alternative embodiments, the entire substrate is removed before forming the strain inducing material.

A dicing die attach film containing a dicing film and a die attach film stacked on the dicing film, wherein the die attach film contains an organic solvent having a boiling point of 100° C. or more and less than 150° C. and a vapor pressure of 50 mmHg or less, and wherein an amount of the organic solvent in the die attach film satisfies the following (a):

(a) when 1.0 g of the die attach film is immersed in 10.0 mL of acetone at 4° C. for 24 hours, an amount of the organic solvent extracted into the acetone is 800 μg or less.

The invention provides an electronic device package and fabrication method thereof. The electronic device package includes a sensor chip. An upper surface of the sensor chip comprises a sensing film. A covering plate having an opening structure covers the upper surface of the sensor chip. A cavity is between the covering plate and the sensor chip, corresponding to a position of the sensing film, where the cavity communicates with the opening structure. A spacer is between the covering plate and the sensor chip, surrounding the cavity. A pressure releasing region is between the spacer and the sensing film.

It is an object of the present invention to provide a film for semiconductor back surface having reworkability, and an application of the film. A film for semiconductor back surface has: an adhering strength at 70° C. of 7 N/10 mm or less to a wafer before the film is thermally cured; and a rupture elongation at 25° C. of 700% or less. The film for semiconductor back surface preferably has a degree of swelling due to ethanol of 1% by weight or more. The film for semiconductor back surface preferably contains an acrylic resin.

The present invention relates to a film for semiconductor device production, which includes: a separator; and a plurality of adhesive layer-attached dicing tapes each including a dicing tape and an adhesive layer laminated on the dicing tape, which are laminated on the separator at a predetermined interval in such a manner that the adhesive layer attaches to the separator, in which the separator has a cut formed along the outer periphery of the dicing tape, and the depth of the cut is at most ⅔ of the thickness of the separator.

A thermosetting sheet according to the present invention includes: a thermosetting resin; a thermoplastic resin; and conductive particles. The conductive particles includes silver particles having an average particle size D.sub.50 of 0.01 μm or more and 10 μm or less, and having a circularity in cross section of 0.7 or more. The thermosetting sheet has a viscosity at 100° C. of 20 kPa.Math.s or more and 3000 kPa.Math.s or less.

A semiconductor device includes a first substrate structure having a first substrate, circuit elements disposed on the first substrate, and first bonding pads disposed on the circuit elements. A second substrate structure is connected to the first substrate structure. The second substrate structure includes a second substrate having first and second surfaces, first and second conductive layers spaced apart from each other, a pad insulating layer having an opening exposing a portion of the second conductive layer and gate electrodes stacked to be spaced apart from each other in a first direction and electrically connected to the circuit elements. First contact plugs extend on the second surface in the first direction and connect to the gate electrodes. A second contact plug extends on the second surface in the first direction and electrically connects to the second conductive layer. Second bonding pads electrically connect to the first and second contact plugs.

Provided in a semiconductor package substrate including a semiconductor chip including a connection pad, an encapsulant encapsulating at least a portion of the semiconductor chip, a connection member disposed on the semiconductor chip and the encapsulant, the connection member including a redistribution layer that is electrically connected to the connection pad, a first passivation layer disposed on the connection member, and an adhesive layer disposed on at least one of a top surface of the encapsulant and a bottom surface of the first passivation layer in a region outside of the semiconductor chip.

A die includes a substrate, a conductive pad, a connector and a protection layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector includes a seed layer and a conductive post. The protection layer laterally covers the connector. Topmost surfaces of the seed layer and the conductive post and a top surface of the protection layer are level with each other.

A radiofrequency device includes a buried insulation layer, a transistor, a contact structure, a connection bump, an interlayer dielectric layer, and a mold compound layer. The buried insulation layer has a first side and a second side opposite to the first side in a thickness direction of the buried insulation layer. The transistor is disposed on the first side of the buried insulation layer. The contact structure penetrates the buried insulation layer and is electrically connected with the transistor. The connection bump is disposed on the second side of the buried insulation layer and electrically connected with the contact structure. The interlayer dielectric layer is disposed on the first side of the buried insulation layer and covers the transistor. The mold compound layer is disposed on the interlayer dielectric layer. The mold compound layer may be used to improve operation performance and reduce manufacturing cost of the radiofrequency device.